LF3320QC12 查看數據表（PDF） - LOGIC Devices

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LF3320QC12

Horizontal Digital Image Filter

LOGIC Devices 

DEVICES INCORPORATED

LF3320

Horizontal Digital Image Filter

After the last data value is loaded, the

interface will expect a new address

value on the next clock cycle. After the

next address value is loaded, data

loading will begin again as previously

discussed. As long as data is loaded

into the interface, LDA must remain

LOW. After all desired coefficient banks

and Configuration/Control registers are

loaded with data, the LF InterfaceTM

must be disabled. This is done by

setting LDA HIGH on the clock cycle

after the clock cycle which latches the

last data value. It is important that the

LF InterfaceTM remain disabled when

not loading data into it.

The Filter A coefficient banks may only be

loaded with the Filter A LF InterfaceTM and

the Filter B coefficient banks may only be

loadedwiththe Filter B LF InterfaceTM.

The Configuration and Control

registers may be loaded with either the

Filter A or B LF InterfacesTM.

Since both LF InterfacesTM operate

independently of each other, both LF

InterfacesTM can load data into their

respective coefficient banks at the same

time. Or, one LF InterfaceTM can load

the Configuration/Control registers

while the other loads it’s respective

coefficient banks. If both LF

InterfacesTM are used to load a Configu-

ration or Control register at the same

time, the Filter B LF InterfaceTM will be

given priority over the Filter A LF

InterfaceTM. For example, if the Filter A

LF InterfaceTM attempts to load data

into a configuration register at the

same time that the Filter B LF

InterfaceTM attempts to load a Filter A

round register, the Filter B LF

InterfaceTM will be allowed to load the

round register while the Filter A LF

InterfaceTM will not be allowed to load

the configuration register. However,

the Filter A LF InterfaceTM will

continue to function as if the write

occurred.

TABLE 8. CFA/CFB11-9 DECODE

11 10 9 DESCRIPTION

0 0 0 Coefficient Banks

0 0 1 Configuration Registers

0 1 0 Filter A Select Registers

0 1 1 Filter B Select Registers

1 0 0 Filter A Round Registers

1 0 1 Filter B Round Registers

1 1 0 Filter A Limit Registers

1 1 1 Filter B Limit Registers

FIGURE 20. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION

CONFIGURATION REGISTER

SELECT REGISTER

CLK

PAUSEA/PAUSEB

LDA/LDB

CFA/CFB11-0

ADDR1

W1

DATA1

ADDR2

W1: Configuration Register loaded with new data on this rising clock edge.

W2: Select Register loaded with new data on this rising clock edge.

W2

DATA1

FIGURE 21. ROUND REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION

ROUND REGISTER

CLK

PAUSEA/PAUSEB

LDA/LDB

CFA/CFB11-0

ADDR1

DATA1

DATA2

W1: Round Register loaded with new data on this rising clock edge.

DATA3

W1

DATA4

Video Imaging Products

2-17

08/16/2000–LDS.3320-N

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