LF3310QC12 查看數據表（PDF） - LOGIC Devices

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LF3310QC12

Horizontal / Vertical Digital Image Filter

LOGIC Devices 

DEVICES INCORPORATED

LF3310

Horizontal / Vertical Digital Image Filter

FIGURE 8. SYMMETRIC COEFFICIENT SET EXAMPLES

87654321

Even-Tap, Even-Symmetric

Coefficient Set

7654321

Odd-Tap, Even-Symmetric

Coefficient Set

8765

4321

Even-Tap, Odd-Symmetric

Coefficient Set

FIGURE 9. I/D REGISTER DATA PATHS

A

B

ALU

A

B

ALU

A

B

ALU

Delay Stage N–1

Delay Stage N

A

B

ALU

A

B

ALU

A

B

ALU

COEF 7

COEF 6

COEF 7

2

COEF 6

COEF 7

2

COEF 6

EVEN-TAP MODE

ODD-TAP MODE

ODD-TAP INTERLEAVE MODE

the I/D Register length.

The I/D Registers also facilitate using

decimation to increase the number of

filter taps. Decimation by N is

accomplished by reading the horizon-

tal filter’s output once every N clock

cycles. The device supports decima-

tion up to 16:1. With no decimation,

the maximum number of filter taps is

sixteen. When decimating by N, the

number of filter taps becomes 16N

because there are N–1 clock cycles

when the horizontal filter’s output is

not being read. The extra clock cycles

are used to calculate more filter taps.

When decimating, the I/D Registers

should be set to a length equal to the

decimation factor. For example,

when performing a 4:1 decimation,

the I/D Registers should be set to a

length of four. When not decimating

or when only one data set

(non-interleaved data) is fed into the

device, the I/D Registers should be

set to a length of one.

I/D Registers, and line buffers. Both

must be active to enable data loading

in Orthogonal Mode.

I/D Register Data Path Control

HSHEN enables or disables the

loading of data into the forward and

reverse I/D Registers when the device

is in Dimensionally Separate Mode

(see the HSHEN section for a full

discussion). When in Orthogonal

Mode, HSHEN also enables or

disables the loading of data into the

input register (DIN11-0) and the line

buffers.

It is important to note that in

Orthogonal Mode, either HSHEN or

VSHEN can disable the loading of

data into the input register (DIN11-0),

The multiplexer in the middle of the

I/D Register data path controls how

data is fed to the reverse data path.

The forward data path contains

the I/D Registers in which data

flows from left to right in the

block diagram in Figure 1. The

reverse data path contains the I/D

Registers in which data flows from

right to left. When the filter is

configured for an even number of

taps, data from the last I/D Regis-

ter in the forward data path is fed

into the first I/D Register in the

reverse data path (see Figure 9).

Video Imaging Products

7

11/08/2001-LDS.3310-H

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