HD74LV595A(2004) 查看數據表（PDF） - Renesas Electronics

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HD74LV595A
(Rev.:2004)

8-bit Shift Registers with 3-state Outputs

Renesas Electronics 

HD74LV595A

Switching Characteristics

Item

Maximum

clock frequency

Propagation

delay time

Enable time

Disable time

Setup time

Hold time

Pulse width

Symbol

fmax

tPLH/tPHL

tPHL

tZH

tZL

tHZ

tLZ

tSU

th

tw

Ta = 25°C

Min Typ

65 80

60 70

— 11.6

— 14.8

— 10.5

— 13.7

— 11.2

— 14.4

— 10.3

— 12.2

— 7.6

— 14.4

5.5 —

10.0 —

10.0 —

5.0 —

2.0 —

0.5 —

0.5 —

7.0 —

7.0 —

6.0 —

Max

—

—

16.4

19.4

15.3

18.3

16.2

19.2

14.8

17.7

11.5

18.2

—

—

—

—

—

—

—

—

—

—

Ta = –40 to 85°C

Min

Max

Unit

45

—

MHz

40

—

1.0

19.5 ns

1.0

22.5

1.0

18.0

1.0

21.0

1.0

18.2

1.0

21.2

1.0

17.5 ns

1.0

20.5

1.0

13.5 ns

1.0

19.2

5.5

—

ns

10.5 —

11.0 —

5.0

—

2.0

—

ns

0.5

—

0.5

—

7.5

—

ns

7.5

—

6.5

—

Test

Conditions

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

FROM

(Input)

VCC = 2.5 ± 0.2 V

TO

(Output)

SRCLK

RCLK

SRCLK

G

QH'

QA – QH

QH'

QA – QH

SER before SRCLK ↑

SRCLK ↑ before RCLK ↑

SRCLR low before RCLK ↑

SRCLR high (inactive)

before SRCLK ↑

SER after SRCLK ↑

SRCLK ↑ after RCLK ↑

SRCLR low after RCLK ↑

RCLK high or low

SRCLK high or low

SRCLR low

Rev.2.00 Jun. 28, 2004 page 6 of 13

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