BR24E08F 查看數據表（PDF） - ROHM Semiconductor
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BR24E08F Datasheet PDF : 12 Pages
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Memory Ics
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
(11) Sequential read
BR24C08 / F / FJ / FV
S
T
R
A
E
R
SLAVE
A
T
ADDRESS D
DATA(n)
SDA
LINE
1 0 1 0 A2 P1 P0
D7
D0
RA
/C
WK
A
C
K
Fig.16
S
T
O
DATA(n+x)
P
D7
D0
A
A
C
C
K
K
BR24C16 / F / FJ / FV
S
T
R
A
E
R
SLAVE
A
T
ADDRESS D
DATA(n)
SDA
LINE
1 0 1 0 P2 P1 P0
D7
D0
RA
/C
WK
A
C
K
Fig.17
S
T
O
DATA(n+x)
P
D7
D0
A
A
C
C
K
K
BR24E16 / F / FJ / FV
S
T
R
A
E
R
SLAVE
A
T
ADDRESS D
DATA(n)
SDA
LINE
1 0 1 0 A2 A1 A0
D7
D0
RA
/C
WK
A
C
K
Fig.18
S
T
O
DATA(n+x)
P
D7
D0
A
A
C
C
K
K
$ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the
next word address data can be read. [All words can be read]
$ This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) using the SCL signal HIGH.
$ Sequential reading can also be done with a random read.
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