CXA3304N 查看數據表（PDF） - Sony Semiconductor

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CXA3304N

IF IC for ETC

Sony Semiconductor 

CXA3304N

5) Peak hold circuit

This circuit holds the Pin 1 RSSI output voltage peak. Peak hold operation and reset operation are

switched with Pin 13.

Peak hold operation

The input RSSI voltage is held by the Pin 7 capacitor. The held voltage passes through the buffer circuit

and is output to Pin 12. The response characteristics during peak hold operation are determined by the

peak hold charge and leak currents, which are determined inside the IC, and the Pin 7 capacitance value.

The held voltage fluctuates according to the peak hold leak current. This fluctuation becomes larger as the

capacitor value is set smaller. Adjust the reset operation interval and the capacitor value as necessary. In

addition, the hold time can also be shortened by connecting a resistor between Pin 7 and GND.

Reset operation

The charge held by the Pin 7 capacitor is discharged according to the peak hold discharge current which is

determined inside the IC. The discharge time changes according to the capacitor value.

Pin 13 voltage

Function

HI

Reset

LOW

Peak hold

6) COMP2 circuit

This is the carrier sense comparator circuit. The input pin is connected internally to the RSSI PEAK output

(Pin 12). Apply the voltage to be used as the threshold value to Pin 11. The comparator output is an open

collector output, and should be connected to the power supply, etc., via a pull-up resistor. Set the

connected power supply to the Pin 9 potential or lower.

—9—

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