AD6402 查看數據表（PDF） - Analog Devices
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AD6402 Datasheet PDF : 8 Pages
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AD6402–SPECIFICATIONS
Parameter
Conditions
AD6402ARS
Min Typ
Max Units
IF BANDPASS FILTER
Center Frequency Rejection
Stop Band Rejection
REFIN = 13.824 MHz, REFSEL <0.2 VCC
FO ± 3.0 MHz
FO ± 4.7 MHz
FO ± 6.0 MHz
20.736
7
13
16
30
MHz
dBc
dBc
dBc
dBc
RECEIVER
Sensitivity
FM Modulated 576 kHz, FM Deviation 288 kHz
–80
dBm
BT = 0.5, Demod Output SNR = 10 dB, RS = 150 Ω
RSSI
Low
VOUT = 0.2 V, RS = 150 Ω
–85
dBm
OBSOLETE High
Slope
Output Impedance
DEMODULATOR
Gain
Offset
Lock Time
DATA FILTER OP AMP
Gain
Slew Rate
Gain Bandwidth
Output Swing Low
Output Swing High
Output Impedance
IF VCO
Frequency
SSB Phase Noise
Output Power
VOUT = 1.8 V, RS = 150 Ω
See Figure 4
At Data Filter Output
Referred to SLREF
From SLEEP Mode
From RXLOCK Mode
CLOAD = 30 pF
CLOAD = 30 pF
Note 1
@ 5 MHz Offset
Differential RLOAD = 300 Ω
1.2
–200
–5
dBm
20
mV/dB
4
kΩ
1.55 V/MHz
+200 mV
200
µs
20
µs
2
8
15
0.2
VCC–0.2
50
V/µs
MHz
V
V
Ω
131
–139
–12
MHz
dBc/Hz
dBm
2nd Harmonic
–22
dB
3rd Harmonic
–24
dB
TRANSMIT FILTER OP AMP
Open Loop Gain
Unity Gain Bandwidth
Output Slew Rate
Minimum Input Voltage
Maximum Input Voltage
Minimum Output Voltage
Maximum Output Voltage
POWER CONTROL
Logical High Threshold
Logical Low Threshold
Turn-On Response Time
CLOAD = 30 pF
CLOAD = 30 pF
VCC Steady State
75
12
5
1
VCC–0.2
0.2
VCC–0.2
0.8 × VCC
0.2 × VCC
0.5
dB
MHz
V/µs
V
V
V
V
V
V
µs
VOLTAGE REFERENCE
SLREF
1.3
1.5
V
SUPPLY REGULATOR
Output Voltage
Turn-On Time
Line Regulation
Load Regulation
For Battery Voltages from 3.1 V to 4.5 V
1 mV Settling, CLOAD = 100 nF
200 mV Battery Step; 5 mV Settling
10 µA to 30 mA Step; 5 mV Settling
2.75
200
1
200
2.95 V
µs
µs
µs
POWER SUPPLY
Supply Current
All VCC at 2.85 V
RXLOCKP
RXLOCK
RXDEMOD
TRANSMIT
STANDBY
SLEEP
30
mA
17
mA
26
mA
6
mA
300
µA
10
µA
NOTES
1Using test tank circuit as shown.
Specifications subject to change without notice.
–2–
REV. 0
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