AD6402 查看數據表（PDF） - Analog Devices

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AD6402

IF Transceiver Subsystem

Analog Devices 

AD6402

RECOMMENDED OPERATING CONDITIONS

VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 V–4.5 V

PIN CONFIGURATION

IFVCC1, IFVCC2, PLLVCC . . . . . . . . . . . . . . . . . . . .2.85 V

Operating Temperature Range . . . . . . . . . . . –25°C to +85°C

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature, Soldering (60 sec) . . . . . . . . . . . . +300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended rating conditions for extended periods may affect device

TXOUTB 1

28 TXOUT

MODOUT 2

27 REFSEL

FMMOD2 3

26 IFVCC1

FMMOD1 4

25 IFIN

VCOGND 5 AD6402 24 IFGND

VCO 6 TOP VIEW 23 RSSI

VREG 7 (Not to Scale) 22 IFVCC2

VBAT 8

21 PLLGND

CTL3 9

20 PLLVCC

reliability.

CTL2 10

19 SLREF

OBSOLETE Thermal Characteristics:

28-lead SSOP package: θJA = 109°C/W.

ORDERING GUIDE

Model

AD6402ARS

AD6402ARS-REEL

Temperature

Range

–25°C to +85°C

–25°C to +85°C

Package

Description

28-Lead SSOP

28-Lead SSOP

CTL1 11

CFILT 12

COFF 13

REXT 14

Pin Mnemonic

1

TXOUTB

2

MODOUT

3

FMMOD2

4

FMMOD1

PIN FUNCTION DESCRIPTIONS

Function

Transmit IF VCO Buffer Inverting Output

Frequency Modulator Filter Op Amp Output

Frequency Modulator Filter Op Amp Noninverting input

Frequency Modulator Filter Op Amp Inverting input

18 DOUT

17 DFILP

16 PLLOUT

15 REFIN

5

VCOGND

IF VCO Ground

6

VCO

IF VCO Tank Connection

7

VREG

Regulated Supply Output for RF VCO (Supplies Internal IF VCO, Mode Control, Bandgap Reference,

and COFF Buffer)

8

VBAT

Battery Supply Voltage Input to Internal Regulator and COFF Charge Pump

9

CTL3

Mode Control Input 3, CMOS Logical Level

10 CTL2

Mode Control Input 2, CMOS Logical Level

11 CTL1

Mode Control Input 1, CMOS Logical Level

12 CFILT

PLL Demodulator Loop Filter Capacitor

13 COFF

PLL Demodulator Frequency Offset Voltage Track/Hold Capacitor

14 REXT

External Current-Setting Resistor

15 REFIN

Baseband Reference Frequency Input, 100 mV p-p, AC Coupled

16 PLLOUT

PLL Demodulator Output

17 DFILP

Data Filter Voltage-Follower Input

18 DOUT

Data Filter Voltage-Follower Output

19 SLREF

PLL Demodulator Output DC Reference Voltage

20 PLLVCC

PLL Demodulator and Data Filter Supply Input

21 PLLGND

PLL Demodulator and Data Filter Ground

22 IFVCC2

IF Limiter Supply Input 1

23 RSSI

RSSI Output

24 IFGND

IF Stage, Mixer, Band Pass Filter, IF VCO Buffer, Tx Op Amp, Mode Control, and Regulator Ground

25 IFIN

26 IFVCC1

IF Mixer Input, ZO = 150 Z

IF Mixer, Limiter 1, IF Filter, IF VCO Buffer

27 REFSEL

Reference Frequency Select; IF = 1.5× or 2.5× Reference Frequency, CMOS Logical Level Input

28 TXOUT

Transmit IF VCO Buffer Output

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD6402 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–3–

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