AD5220 查看數據表（PDF） - Analog Devices
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AD5220 Datasheet PDF : 11 Pages
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AD5220–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VDD = +3 V ؎ 10% or +5 V ؎ 10%, VA = +VDD, VB = 0 V, –40؇C < TA < +85؇C unless
otherwise noted)
Parameter
Symbol Conditions
Min
Typ1 Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
R-DNL RWB, VA = NC, RAB = 10 kΩ
Resistor Nonlinearity2
R-INL
RWB, VA = NC, RAB = 50 kΩ or 100 kΩ
RWB, VA = NC, RAB = 10 kΩ
RWB, VA = NC, RAB = 50 kΩ or 100 kΩ
Nominal Resistor Tolerance
∆R
TA = +25°C
Resistance Temperature Coefficient
∆RAB/∆T VAB = VDD, Wiper = No Connect
Wiper Resistance
RW
IW = VDD/R, VDD = +3 V or +5 V
–1
± 0.4 +1
LSB
–0.5
± 0.1 +0.5 LSB
–1
± 0.5 +1
LSB
–0.5
± 0.1 +0.5 LSB
–30
+30 %
800
ppm/°C
40
100 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
Integral Nonlinearity3
INL
Differential Nonlinearity Error3
DNL
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
∆VW/∆T
VWFSE
VWZSE
RAB = 10 kΩ
RAB = 50 kΩ, 100 kΩ
RAB = 10 kΩ
RAB = 50 kΩ, 100 kΩ
Code = 40H
Code = 7FH
Code = 00H
7
Bits
–1
± 0.5 +1
LSB
–0.5
± 0.2 +0.5 LSB
–1
± 0.4 +1
LSB
–0.5
± 0.1 +0.5 LSB
20
ppm/°C
–2
–0.5 0
LSB
0
+0.5 +1
LSB
RESISTOR TERMINALS
Voltage Range4
Capacitance5 A, B
Capacitance5 W
Common-Mode Leakage
VA, VB, VW
0
CA, CB
f = 1 MHz, Measured to GND, Code = 40H
CW
f = 1 MHz, Measured to GND, Code = 40H
ICM
VA = VB = VW
VDD
V
10
pF
48
pF
7.5
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
Input Logic Low
VIL
Input Current
IIL
Input Capacitance5
CIL
VDD = +5 V/+3 V
VDD = +5 V/+3 V
VIN = 0 V or +5 V
2.4/2.1
5
V
0.8/0.6 V
±1
µA
pF
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation6
Power Supply Sensitivity
VDD
IDD
PDISS
PSS
VIH = +5 V or VIL = 0 V, VDD = +5 V
VIH = +5 V or VIL = 0 V, VDD = +5 V
2.7
5.5 V
15
40
µA
75
200 µW
0.004 0.015 %/%
DYNAMIC CHARACTERISTICS5, 7, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
BW_10K
BW_50K
BW_100K
THDW
tS
eNWB
RAB = 10 kΩ, Code = 40H
RAB = 50 kΩ, Code = 40H
RAB = 100 kΩ, Code = 40H
VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz
VA = VDD, VB = 0 V, 50% of Final Value,
10K/50K/100K
RWB = 5 kΩ, f = 1 kHz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 9
Input Clock Pulsewidth
tCH, tCL Clock Level High or Low
25
CS to CLK Setup Time
tCSS
20
CS Rise to Clock Hold Time
tCSH
20
U/D to Clock Fall Setup Time
tUDS
10
650
142
69
0.002
0.6/3/6
14
kHz
kHz
kHz
%
µs
nV/√Hz
ns
ns
ns
ns
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5Guaranteed by design and not subject to production test.
6PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8All dynamic characteristics use VDD = +5 V.
9See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V.
Specifications subject to change without notice.
–2–
REV. A
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