1046 查看數據表（PDF） - Linear Technology

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1046

"Inductorless" +5V to -5V Converter

Linear Technology 

LTC1046

APPLICATI S I FOR ATIO

By connecting the BOOST (Pin 1) to V+, the charge and

discharge current is increased and, hence, the frequency

is increased by approximately three times. Increasing the

frequency will decrease output impedance and ripple for

higher load currents.

Loading Pin 7 with more capacitance will lower the fre-

quency. Using the BOOST pin in conjunction with external

capacitance on Pin 7 allows user selection of the fre-

quency over a wide range.

Driving the LTC1046 from an external frequency source

can be easily achieved by driving Pin 7 and leaving the

BOOST pin open, as shown in Figure 6. The output current

from Pin 7 is small, typically 15µA, so a logic gate is

capable of driving this current. The choice of using a CMOS

logic gate is best because it can operate over a wide supply

voltage range (3V to 15V) and has enough voltage swing

to drive the internal Schmitt trigger shown in Figure 5. For

5V applications, a TTL logic gate can be used by simply

adding an external pull-up resistor (see Figure 6).

Capacitor Selection

While the exact values of CIN and COUT are noncritical,

good quality, low ESR capacitors such as solid tantalum

are necessary to minimize voltage losses at high currents.

For CIN the effect of the ESR of the capacitor will be

multiplied by four, due to the fact that switch currents are

approximately two times higher than output current, and

losses will occur on both the charge and discharge cycle.

This means that using a capacitor with 1Ω of ESR for CIN

will have the same effect as increasing the output imped-

ance of the LTC1046 by 4Ω. This represents a significant

increase in the voltage losses. For COUT the effect of ESR

is less dramatic. COUT is alternately charged and dis-

charged at a current approximately equal to the output

current, and the ESR of the capacitor will cause a step

function to occur, in the output ripple, at the switch

transitions. This step function will degrade the output

regulation for changes in output load current, and should

be avoided. Realizing that large value tantalum capacitors

can be expensive, a technique that can be used is to

parallel a smaller tantalum capacitor with a large alumi-

num electrolytic capacitor to gain both low ESR and

reasonable cost. Where physical size is a concern some

of the newer chip type surface mount tantalum capacitors

can be used. These capacitors are normally rated at

working voltages in the 10V to 20V range and exhibit very

low ESR (in the range of 0.1Ω).

REQUIRED FOR TTL LOGIC

LTC1046

1

NC BOOST

V+ 8

+

C1

2 CAP +

3

GND

OSC 7

LV 6

4 CAP – VOUT 5

V+

100k

–(V+)

C2

OSC INPUT

1046 F06

Figure 6. External Clocking

6

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