STK12C68-SF55I 查看數據表（PDF） - Unspecified
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STK12C68-SF55I Datasheet PDF : 13 Pages
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STK12C68
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
12
tAVAV
13
tWLWH
14
tELWH
15
tDVWH
16
tWHDX
17
tAVWH
18
tAVWL
19
tWHAX
20
tWLQZ i, j
21
tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
25
35
45
55
ns
tWP Write Pulse Width
20
25
30
45
ns
tCW Chip Enable to End of Write
20
25
30
45
ns
tDW Data Set-up to End of Write
10
12
15
25
ns
tDH Data Hold after End of Write
0
0
0
0
ns
tAW Address Set-up to End of Write
20
25
30
45
ns
tAS Address Set-up to Start of Write
0
0
0
0
ns
tWR Address Hold after End of Write
0
0
0
0
ns
tWZ Write Enable to Output Disable
10
13
14
15
ns
tOW Output Active after End of Write
5
5
5
5
ns
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
ADDRESS
E
12
tAVAV
14
tELWH
19
tWHAX
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
DATA OUT
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledk, l
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
October 2003
4 Document Control # ML0008 rev 0.4
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