A6850KL-T 查看數據表（PDF） - Allegro MicroSystems
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A6850KL-T Datasheet PDF : 9 Pages
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A6850
Dual Channel Switch Interface IC
L Package, 8-Pin SOIC
5.00 .197
4.80 .189
8
Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-012 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
A
B Reference pad layout (reference IPC SOIC127P600-8M);
adjust as necessary to meet application process requirements
1
2
6.20 .244
5.80 .228
0.25 [.010] M B M
A
B
4.00 .157
3.80 .150
8X
0.10 [.004] C
8X
0.51
0.31
.020
.012
0.25 [.010] M C A B
1.27 .050
C
SEATING
PLANE
1.75 .069
1.35 .053
0.25 .010
0.10 .004
2.50 .098
REF
B
4.90 .193
REF
8º
0º
0.25 .010
0.17 .007
1.27 .050
0.40 .016
0.25 .010
SEATING PLANE
GAUGE PLANE
0.65 .026
MAX
1.27 .050
REF
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright©2006 AllegroMicroSystems, Inc.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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