TMC2330AH5C 查看數據表（PDF） - Cadeka Microcircuits LLC.
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TMC2330AH5C Datasheet PDF : 18 Pages
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PRODUCT SPECIFICATION
TMC2330A
Pin Descriptions (continued)
Pin Name
CLK
Pin Number
MQFP
CPGA/PPGA/
MPGA
12
F3
Inputs/Outputs
XRIN15-0
79, 78, 77, 75, 74,
73, 72, 71, 70, 69,
67, 66, 65, 63, 62,
60
F12, F13, G13,
G12, H13, H12,
H11, J13, J12,
K13, K12, L13,
L12, M13, M12,
N13
YPIN31-0
58, 57, 56, 55, 54, L10, N12, N11,
53, 52, 51, 49, 48, M10, L9, N10, M9,
47, 45, 44, 43, 41, N9, M8, N8, N7,
40, 39, 38, 37, 36, M7, N6, M6, N5,
35, 33, 32, 30, 29, M5, N4, L5, M4,
27, 26, 25, 24, 23, N3, M3, N2, M2,
22, 21
N1, L2, M1, L1,
K2, J3, K1, J2, J1
RXOUT15-0
83, 85, 86, 87, 89,
90, 92, 93, 95, 96,
97, 99, 100, 101,
103, 104
D13, D12, C13,
B13, C12, A13,
B12, A12, B11,
A11, B10, A10,
B9, A9, B8, A8
PYOUT15-0
107, 108, 109,
111, 112, 113,
115, 116, 117,
119, 120, 2, 3, 5,
6, 7
A7, A6, B6, A5,
B5, A4, B4, A3,
A2, B3, A1, B2,
B1, C2, C1, D2
Controls
ENXR
59
M11
ENYP1,0
17, 15
G1, G2
Description
The TMC2330A operates from a single clock. All enabled
registers are strobed on the rising edge of CLK, which is
the reference for all timing specifications.
XRIN15-0 is the registered Cartesian X-coordinate or
Polar Magnitude (Radius) 16-bit input data port. XRIN15 is
the MSB.
YPIN31-0 is the registered Cartesian Y-coordinate or Polar
Phase angle 32-bit input data port. The input phase
accumulators are fed through this port in conjunction with
the input enable select ENYP1,0. When RTP is HIGH
(Rectangular-To-Polar), the input accumulators are
normally not used. The 16 MSBs of YPIN are the input
port, and the lower 16 bits become “don’t cares” if ACC = 00.
YPIN31 is the MSB.
RXOUT15-0 is the registered Polar Magnitude (Radius) or
X-coordinate 16-bit output data port. This output is forced
into the high-impedance state when OERX=HIGH.
RXOUT15 is the MSB.
PYOUT15-0 is the registered Polar Phase angle or
Cartesian Y-coordinate 16-bit output data port. This output
is forced to the high-impedance state when OEPY=HIGH.
PYOUT15 is the MSB.
The value presented to the input port XRIN is latched into
the input registers on the current clock when ENXR is
HIGH. When ENXR is LOW, the value stored in the
register remains unchanged.
The value presented to the YPIN input port is latched into
the phase accumulator input registers on the current
clock, as determined by the control inputs ENYP1,0, as
shown below:
Register Operation
ENYP1,0 M
C
00
hold
hold
01
load
hold
10
hold
load
11
clear
load
where C is the Carrier register and M is the Modulation
register, and 0=LOW, 1=HIGH. See the Functional Block
Diagram.
6
REV. 1.1.8 10/31/00
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