ML4621 查看數據表（PDF） - Micro Linear Corporation

零件编号

产品描述 (功能)

生产厂家

ML4621

Data Quantizer

Micro Linear Corporation 

PIN DESCRIPTION (Pin Number in Parenthesis is for DIP Version)

PIN NAME

FUNCTION

1 (1) ECL LINK MON ECL link monitor output. Signal

is low when the VIN+ and VIN–

inputs exceed the minimum

threshold set by a voltage on

VTH ADJ. Signal is high when

input signal level is below that

threshold.

2 (2) TTL LINK MON TTL link monitor output. Same

logic function as the ECL LINK

MON. Capable of driving a

10mA LED indicator. This pin is

normally tied to CMP ENABLE.

3 (3) CMP ENABLE

Low voltage at this TTL input

enables both the ECL and TTL

outputs. A high TTL voltage

disables the comparator output

with ECL+ high, ECL– low, and

TTL OUT high.

5 (4) VIN–

This input should be capacitively

coupled to the input source or to

ground. (Input resistance is

approximately 8kΩ).

PIN NAME

14(12) CMP–

16(13) ECL–

17(14) ECL+

18(15) GND TTL

19(16) VCC TTL

20(17) TTL OUT

21(18) GND

6 (5) VIN+

8 (6) VDC

9 (7) CF2

This input should be capacitively

coupled to the input source or to

ground. (Input resistance is

approximately 8kΩ).

An external capacitor on this pin

integrates an error signal which

nulls the offset of the input

amplifier. If the DC feedback

loop is not being used, this pin

should be connected to VREF.

A capacitor from this pin to

ground controls the maximum

bandwidth of the amplifier to

accommodate lower operating

frequencies.

22(19) VTH ADJ

23(20) VREF

24(21) CPEAK

26(22) ISET

10 (8) CF1

11 (9) VOUT-

12 (10) VOUT+

13 (11) CMP+

The capacitor on this pin should

match the one on CF2.

Negative output of the amplifier,

which is normally tied to CMP–.

Positive output of the amplifier,

which is normally tied to CMP+.

Comparator input pin. Open base

configuration relies on the DC

bias of the amp output to set

proper DC operating voltage.

Reestablish voltage if filtering is

used between VOUT+ and CMP+.

27(23) INOM

28(24) VCC

ML4621

FUNCTION

Comparator input pin. Open base

configuration relies on the DC

bias of the amp output to set the

proper DC operating voltage.

Reestablish voltage if filtering is

used between VOUT– and CMP–.

ECL comparator negative output.

ECL comparator positive outout.

Negative supply for the TTL

comparator stage. If the TTL

output is not necessary, connect

GND TTL and VCC TTL to VCC.

Positive supply for the TTL

comparator stage. If the TTL

output is not necessary, connect

GND TTL and VCC TTL to VCC.

TTL data output (totem pole type

output stage).

Negative supply. Connect to –

5.2V for ECL operation, or to

source ground for TTL operation.

This input sets the minimum

amplitude of the input signal

required to cause the link

monitors to go low.

A 2.5V reference with respect to

GND.

A capacitor from this pin to GND

determines the link monitor

response time.

Current into an internal diode

connected between this pin and

GND is turned around and pulled

from CPEAK. This pin is normally

connected to INOM.

Sets a current of approximately

125µA when connected to ISET.

Positive supply. Connect to

source ground for ECL operation,

or to 5V for TTL operation.

3

Share Link: