SDA5648 查看數據表（PDF） - Siemens AG

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SDA5648

Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder

Siemens AG 

SDA 5648

SDA 5648X

Control Register

Bit Number

7

6

5

4

3

2

1

0

T4

T3

T2

T1

T0

DIS PDC/ FOR1/

VPS FOR2

Default: All bits are set to 0 on power-up.

Bit 0: Determines, which kind of data is accessed via the I2C-Bus when PDC mode is active.

0

BDSP

8/ 30/ 2

data accessible

Value

1

BDSP 8/ 30/ 1 or

header row

data accessible (refer to description of Bit 2)

Bit 1: Determines the operating mode.

0

VPS mode active

Value

1

PDC mode active

Bits 2 through 7 are used for test purposes.

DIS: Don‘t care.

Bits 3 through 7 must not be changed for normal operation by user software!

Read Mode

For reading from the PDC decoder, the following format has to be used.

START Chipaddress Read Mode AS 1st Byte AM …

Last

Byte

NAM STOP

Semiconductor Group

27

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