LF3304 查看數據表（PDF） - LOGIC Devices Incorporated
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LF3304 Datasheet PDF : 12 Pages
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DEVICES INCORPORATED
LF3304
Dual Line Buffer/FIFO
LINE BUFFER MODE
SIGNAL DEFINITIONS
Power
VCC and GND
+3.3 V power supply. All pins must
be connected.
Clocks
WCLKA — Write Clock A
WCLKA and RCLKA must be tied
together for RAM Array A to properly
operate as a Line Buffer. The rising edge
of xCLKA strobes all appropriate
enabled registers.
RCLKA — Read Clock A
See WCLKA description.
WCLKB — Write Clock B
WCLKB and RCLKB must be tied
together for RAM Array B to properly
operate as a Line Buffer. The rising
edge of xCLKB strobes all appropriate
enabled registers.
RCLKB — Read Clock B
See WCLKB description.
Inputs
AIN11-0 — Data Input A
AIN11-0 is the 12-bit registered data
input port.
BIN11-0 — Data Input B
BIN11-0 is the 12-bit registered data
input port.
LENGTH11-0 — Line Buffer Length
The 12-bit value is used to specify the
length of each of the RAM Arrays. An
integer value ranging from 0 to 4095 is
used to select a delay ranging from 2 to
4097 clock cycles. The value placed on
LENGTH11-0 is equal to the desired delay
minus 8. To set the length of RAM Array A
the data presented on LENGTH11-0 is
loaded into the device on the active edge of
WCLKA in conjunction with LDA being
driven LOW. To set the length of RAM
Array B the data presented on
LENGTH11-0 is loaded into the device
on the active edge of WCLKB in
conjunction with LDB being driven
LOW. If an equal length is desired for
both RAM Arrays, the data presented
on LENGTH11-0 is loaded into the
device on the active edge of WCLK
(WCLKA and WCLKB tied together) in
conjuction with LDx (LDA and LDB
tied together) being driven LOW.
MODE1-0 — Mode Select
The mode select inputs determine the
operating mode of the LF3304 (Table 1) for
data being input on the next clock cycle.
When switching between modes, the
internal pipeline latencies of the device
must be observed. After switching
operating modes, either the user must
allow enough clock clycles to pass to flush
the internal RAM Array or RWx and RRx
must be driven LOW together before valid
data will appear on the outputs.
Controls
LDA — RAM Array A Load
When LDA is LOW, data on
LENGTH11-0 is latched in the length
register on the rising edge of xCLKA.
LDB — RAM Array B Load
When LDB is LOW, data on
LENGTH11-0 is latched in the length
register on the rising edge of xCLKB.
WENA — Write Enable A
Driving WENA LOW places the device in
programmable delay mode and driving
WENA HIGH places RAM Array A in
recirculate mode (programmable circular
buffer). When in recirculate mode, the
write pointer position remains fixed while
data on AIN11-0 is ignored. When
switching back from recirculate mode to
TABLE 1. DEVICE CONFIGURATION
MODE1-0
00
Mode Select
Dual Line Buffer
01
Cascaded Line Buffer
10
Dual FIFO
11
Reserved
delay mode, RWA and RRA should be
brought LOW to properly reset the Write
and Read pointers.
RENA — Read Enable B
In Line Buffer mode, RENA must be
kept LOW.
WENB — Write Enable B
Driving WENB LOW places the device in
programmable delay mode and driving
WENB HIGH places RAM Array B in
recirculate mode (programmable circular
buffer). When in recirculate mode, the
write pointer position remains fixed
while data on BIN11-0 is ignored. When
switching back from recirculate mode to
delay mode, RWB and RRB should be
brought LOW to properly reset the Write
and Read pointers.
RENB — Read Enable B
In Line Buffer mode, RENB must be
kept LOW.
RWA — Reset Write A
The write address pointer is reset to the
first physical location when RWA is set
LOW. After power up, the LF3304
requires a Reset Write for initialization
because the write address pointer is not
defined at that time.
RRA — Reset Read A
The read address pointer is reset to the
first physical location when RRA is set
LOW. After power up, the LF3304
requires a Reset Read for initialization
because the read address pointer is not
defined at that time.
Video Imaging Products
2
808/16/2000–LDS.3304-F
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