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NC7SZ57 查看數據表(PDF) - Fairchild Semiconductor

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NC7SZ57 Datasheet PDF : 13 Pages
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Function Table
Inputs
I2
I1
I0
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H = HIGH Logic Level
L = LOW Logic Level
NC7SZ57
Y = (I0) • (I2) + (I1) • (I2)
H
L
H
L
L
L
H
H
Function Selection Table
2-Input Logic Function
2-Input AND
2-Input AND with Inverted Input
2-Input AND with Both Inputs Inverted
2-Input NAND
2-Input NAND with Inverted Input
2-Input NAND with Both Inputs Inverted
2-Input OR
2-Input OR with Inverted Input
2-Input OR with Both Inputs Inverted
2-Input NOR
2-Input NOR with Inverted Input
2-Input NOR with Both Inputs Inverted
2-Input XOR
2-Input XNOR
Device Selection
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
NC7SZ57
NC7SZ58
Y = (I0) • (I2) + (I1) • (I2)
L
H
L
H
H
H
L
L
Connection Configuration
Figure 4
Figure 10, Figure 11
Figure 7
Figure 9
Figure 5, Figure 6
Figure 12
Figure 12
Figure 5, Figure 6
Figure 9
Figure 7
Figure 9, Figure 10
Figure 4
Figure 13
Figure 8
© 2000 Fairchild Semiconductor Corporation
NC7SZ57 • NC7SZ58 • Rev. 1.0.4
3
www.fairchildsemi.com

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