DG411 查看數據表（PDF） - Maxim Integrated
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DG411 Datasheet PDF : 12 Pages
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Improved, Quad,
SPST Analog Switches
______________________________________________Timing Diagrams/Test Circuits
+3V
LOGIC
INPUT 0V
50%
tr < 20ns
tf < 20ns
SWITCH 0V
OUTPUT
tOFF
VOUT
0.9 x VOUT
tON
0.9 x VOUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 2. Switching-Time
SWITCH
INPUT
+5V
VL
S1
IN1
+15V
V+
D1
DG411
DG412
DG413
SWITCH OUTPUT
VOUT
RL
CL
300Ω
35pF
LOGIC
INPUT
GND
V-
0V
-15V
REPEAT TEST FOR IN AND S, FOR LOAD
CONDITIONS, SEE Electrical Characteristics.
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VS
RL
RL + RDS(ON)
LOGIC +3V
INPUT
0V
SWITCH
OUTPUT 1
(VO1)
0V
SWITCH
OUTPUT 2
(VO2)
0V
50%
0.9 x VOUT1
0.9 x VOUT2
tD
tD
Figure 3. DG413 Break-Before-Make
VS1 = +10V
VS2 = +10V
+5V
VL
S1
S2
+15V
V+ D1
D2
DG413
VOUT2 RL1
VOUT1
CL1
LOGIC
INPUT
IN
RL2
CL2
GND
V-
-15V
RL = 300Ω
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. CL = 35pF
VOUT
IN
OFF
ΔVOUT
OFF
ON
ON
OFF
OFF
IN
Q = (ΔVOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge-Injection
VGEN
+5V
VL
RGEN
S
+15V
V+
D
GND
IN
V-
-15V
VIN = +3V
DG411
DG412
DG413
VOUT
CL
_______________________________________________________________________________________ 7
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