ST75C520
I.7 - Power Supply
Symbol
VDD
GND
AVDD
AGNDT
AGNDR
Parameter
Digital +5V (Pin 9, 25, 41). To be connected to AVDD (see below).
Digital Ground (Pin 8, 24, 40). To be connected to AGNDT and AGNDR (see below).
Analog +5V (Pin 62). To be connected to VDD (see below).
Analog Transmit Ground (Pin 64). To be connected to GND (see below).
Analog Receive Ground (Pin 59). To be connected to GND (see below).
AGNDT and AGNDR must be connected together as close as possible to the chip.
GND and AGNDR board plans should be separated, then connected together as close as possible to the
chip, at a single point. Similarly VDD and AVDD must ne connected as close as possible to the chip, at a
single point.
II - BLOCK DIAGRAMS
II.1 - Functional Block Diagram
ST75C520
SD [0..7]
(26 to 33)
DUAL RAM
INTERFACE
15
16 14
HDLC
TX
MUX
V.17, V.29, V.27
FAX TRANSMITTER
TX
ANALOG
DPLL
HDLC
RX
V.17, V.29, V.27
FAX RECEIVER
RX
ANALOG
SINTR 38
HANDSHAKE AND
STATUS REPORT
V.24
INTERFACE
RING
DETECTOR
TONE
DETECTOR
V.21 FLAG
DETECTOR
13 12 11
10
1 TXA2
2 TXA1
60 RXA1
61 RXA2
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