ST75C520 查看數據表（PDF） - STMicroelectronics
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ST75C520 Datasheet PDF : 45 Pages
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ST75C520
III.3 - AC Electrical Characteristics
III.3.1 - Dual Port RAM Host Timing
WRITE-CYCLE TIMING
NSCS
SA[0..6]
Valid Address
SR/NW
NSDS
SD[0..7]
NSDTACK
NSINTR
1
7
4
8
35
Valid Data
IN
2
6
11
READ-CYCLE TIMING
Valid Address
1
9
4
12
10
5
Valid Data
OUT
2
6
SR/NW (= NWRITE)
NSDS (= NREAD)
Number
1
2
3
4
5
6
7
8
9
10
11
12
Description
Address and Control Set-up Time
SDTACK Acknowledge
Data Set-up Time
Address and Control Hold Time
Data Hold Time
SDTACK Hold Time
Write Enable Low State
Access Inhibition High State (see Note)
Read Enable Low State
Read Data Access
SINTR Clear Delay
Data Valid to Tristate
Min. Typ. Max. Unit
5
ns
20
ns
10
ns
0
ns
5
ns
0
ns
45
ns
70
ns
45
ns
35
ns
50
ns
15
ns
Note : A minimum delay of 70ns is required only from the rizing edge of NWRITE to the falling edge of the next selected NREAD or NWRITE.
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