V292BMC-33LPN 查看數據表（PDF） - QuickLogic Corporation
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V292BMC-33LPN Datasheet PDF : 14 Pages
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V292BMC Rev.D
Table 10: Capacitive Derating for Output and I/O Pins
Output Drive Limit
12 mA
12 mA
Supply voltage
Vcc=5 Volt, Vcc3=3.3 Volt
Vcc=5 Volt, Vcc3=5 Volt
Derating
0.06 ns/pF for loads > 50 pF
0.04 ns/pF for loads > 50 pF
Table 11: Timing Parameters for V292BMC Vcc = 5 Volts +/- 5% and Vcc3 = 5
or 3.38 Volts +/- 5%
Symbol
Description
tC
tCH
tCL
tSU
tH
tH
tRZH
tRHL
tRLH
tRHZ
tEHL
tELH
tIHL
tILH
tARA1
MEMCLK period
MEMCLK high time
MEMCLK low time
Synchronous input setup
Synchronous input hold
Synchronous input hold (RESET#)
RDY 3-state to valid delay
RDY synchronous assertion delay
RDY synchronous de-assertion delay
RDY valid to 3-state delay
ERR synchronous assertion delay
ERR synchronous de-assertion delay
INT synchronous assertion delay
INT synchronous de-assertion delay
Address Input to Row Address output delay
(Interleaved)
tARA2 Address Input to Row Address output delay
(Non-interleaved)
tRAH
tCAV
tCAH
tBCAV
Row address hold from RAS assertion
Column address valid from RAS assertion
Column address hold from CAS assertion
Column address valid delay from previous
CAS assertion (Burst)
tRHL MEMCLK to RAS asserted delay
tRLH MEMCLK to RAS de-asserted delay
tRAS RAS pulse width
tRSH RAS hold from last CAS assertion
tRP RAS precharge time
tCHL MEMCLK to CAS asserted delay
Note
1
1
33 MHz
Min Max
30
12
12
9
1
3
3 13
3 13
3 13
3 10
3 13
3 12
3 13
3 12
3 14
40 MHz
Min Max Units
25
ns
11
ns
11
ns
8
ns
0.5 ns
3 ns
3 10 ns
3 11 ns
3 11 ns
3
7 ns
3 11 ns
3 10 ns
3 11 ns
3 10 ns
3 12 ns
4 18 4 15 ns
2
tM tM+2 tM tM+2 ns
2 tM+1 tM+4 tM+1 tM+4 ns
tC
tC
ns
tC+3
tC+3 ns
3 13 3 11 ns
3 13 3 11 ns
3 3tC-1
3tC-1
ns
4
tN
tN
ns
5 tP-2
tP-2
ns
1
3 13 3 12 ns
10
V292BMC Rev D Data Sheet Rev 3.2
Copyright © 1998, V3 Semiconductor Inc.
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