LTC1503IS8-1.8 查看數據表（PDF） - Linear Technology

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LTC1503IS8-1.8

High Efficiency Inductorless Step-Down DC/DC Converters

Linear Technology 

LTC1503-1.8/LTC1503-2

APPLICATIO S I FOR ATIO

approximately 1.9V. Since the ramp rate on the SHDN/SS

pin controls the ramp rate on VOUT, the average inrush

current can be controlled through selection of CSS and

COUT. For example, a 4.7nF capacitor on SHDN/SS results

in a 4ms ramp time from 0.35V to 1.9V on the pin. If COUT

is 10µF, the 4ms VREF ramp time results in an average

COUT charge current of only 5mA (see Figure 2c).

ON OFF VCTRL

1

VOUT

LTC1503-X

5

SHDN/SS

CSS

1503-1.8/2 F02a

RLOAD

(a)

VCTRL

2V/DIV

VOUT

1V/DIV

LTC1503-2

CSS = 0nF

COUT = 10µF

RLOAD = 50Ω

2ms/DIV

(b)

1503-1.8/2 F02b

VCTRL

2V/DIV

VOUT

1V/DIV

LTC1503-2

CSS = 4.7nF

COUT = 10µF

RLOAD = 50Ω

2ms/DIV

(c)

1503-1.8/2 F02b

Figure 2. Shutdown/Soft-Start Operation

Capacitor Selection

For best performance, it is recommended that low ESR

capacitors be used for CIN and COUT to reduce noise and

ripple. If the ESR of the output capacitor is too high

(> 0.5Ω), both efficiency and output load regulation may

be degraded. The CIN and COUT capacitors should be either

ceramic or tantalum and should be 10µF or greater. If the

input source impedance is very low (< 0.5Ω), CIN may not

be needed. Ceramic capacitors are recommended for the

flying caps C1 and C2 with values of 0.47µF to 2.2µF.

Smaller values may be used in low output current applica-

tions (e.g., IOUT < 10mA). For best performance choose

the same capacitance value for both C1 and C2.

Output Ripple

Normal LTC1503-X operation produces voltage ripple on

the VOUT pin. Output voltage ripple is required for the parts

to regulate. Low frequency ripple exists due to the hyster-

esis in the sense comparator and propagation delays in the

charge pump enable/disable circuits. High frequency ripple

is also present mainly from the ESR (equivalent series

resistance) in the output capacitor. Typical output ripple

(VIN = 3.6V) under maximum load is 25mV peak-to-peak

with a low ESR 10µF output capacitor.

The magnitude of ripple voltage depends on several fac-

tors. High input voltages increase the output ripple since

more charge is delivered to COUT per charging cycle. Large

output current load and/or a small output capacitor (< 10µF)

results in higher ripple due to higher output voltage dV/dt.

High ESR capacitors (ESR > 0.5Ω) on the output pin cause

high frequency voltage spikes on VOUT with every clock

cycle.

There are several ways to reduce the output voltage ripple

(see Figure 3). A larger COUT capacitor (22µF or greater)

will reduce both the low and high frequency ripple due to

the lower COUT charging and discharging dV/dt and the

lower ESR typically found with higher value (larger case

size) capacitors. A low ESR ceramic output capacitor will

minimize the high frequency ripple, but will not reduce the

low frequency ripple unless a high capacitance value is

chosen. A reasonable compromise is to use a 10µF to 22µF

tantalum capacitor in parallel with a 1µF to 3.3µF ceramic

8

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