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NTE3880 查看數據表(PDF) - NTE Electronics

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产品描述 (功能)
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NTE3880 Datasheet PDF : 5 Pages
1 2 3 4 5
Absolute Maximum Ratings:
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
Voltage On Any Pin With Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only functional operation of the device at these
or any other condition above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
DC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Power Supply Current
Input Leakage Current
Tri–State Output Leakage Current in Float
Tri–State Output Leakage Current in Float
Data Bus Leakage Current in Input Mode
VILC
VIHC
VIL
VIH
VOL
VOH
ICC
IL1
ILOH
ILOL
ILD
IOL = 1.8mA
IOH = –250µA
VIN = 0 to VCC
VOUT = 2.4 to VCC
VOUT = 0.4V
0 VIN VCC
–0.3 – 0.80 V
VCC–0.6 – VCC+3 V
–0.3 – 0.8 V
2.0
– VCC V
– 0.4 V
2.4
V
90 200 mA
10 µA
10 µA
– –10 µA
±10 µA
Capacitance: (TA = +25°C, f = 1MHz, unmeasured pins to GND unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Clock Capacitance
Input Capacitance
Output Capacitance
Cφ
CIN
COUT
– – 35 pF
––
5 pF
– – 10 pF
AC Characteristics: (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified)
Parameter
Symbol Signal Test Conditions Min Typ Max Unit
Clock Period
Clock Pulse Width, Clock High
Clock Pulse Width, Clock Low
Clock Rise and Fall Time
Address Output Delay
Data to Float
Address Stable Prior to MRFQ (Memory Cycle)
Address Stable Prior to IOFQ, RD or WR (I/O Cycle)
Address Stable from RD, WR, IORQ, or MREQ
Address Stable from RD or WR During Float
tc
tw (φH)
tw (φL)
tr, tf
tD (AD)
tF (AD)
tacm
taci
tca
tcaf
φ
A0–15 CL = 50pF
25 – Note 2 µs
110 – Note 3 ns
110 – 2000 ns
– 30 ns
– 110 ns
– 90 ns
Note 4 –
ns
Note 5 –
ns
Note 6 –
ns
Note 7 –
ns
Note 2. tc = tw (φH) + tw (φL) + tr + tf.
Note 3. Although static by design, testing guarantees tw (φH) of 200µs maximum.
Note 4. tacm = tw (φH) + tf–65.
Note 5. taci = tc–70.
Note 6. tca = tw (φL) + tr–50.
Note 7. tcaf = tw (φL) + tr–45.

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