NTE3880 查看數據表（PDF） - NTE Electronics

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NTE3880

Integrated Circuit NMOS, 8–Bit Microprocessor (MPU), 4MHz

NTE Electronics 

AC Characteristics (Cont’d): (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified)

Parameter

Symbol Signal Test Conditions Min Typ Max Unit

Data Output Delay

Delay to Float During Write Cycle

tD (D)

tF (D)

D0–7 CL = 50pF

–

– 150 ns

–

– 90 ns

Data Setup Time to Rising Edge of Clock

During M1 Cycle

Data Setup Time to falling Edge of Clock

During M2 to M5

Data Stable Prior to WR (Memory Cycle)

Data Stable Prior to WR (I/O Cycle)

Data Stable From WR

Any Hold Time for Setup Time

MREQ Delay From Falling Edge of Clock,

MREQ Low

tSφ (D)

tdcm

tdci

tcdf

tH

tDLφ (MR)

MREQ CL = 50pF

35

–

50

–

Note 8 –

Note 9 –

Note 10 –

–

–

–

–

– ns

– ns

– ns

– ns

– ns

0 ns

85 ns

MREQ Delay From Rising Edge of Clock, tDHφ (MR)

MREQ High

–

– 85 ns

MREQ Delay From Falling Edge of Clock,

MREQ High

–

– 85 ns

Pulse Width, MREQ Low

Pulse Width, MREQ High

IORQ Delay From Rising Edge of Clock

IORQ Low

tw (MRL)

tw (MRH)

tDLφ (IR)

IORQ CL = 50pF

Note 11 –

Note 12 –

–

–

– ns

– ns

75 ns

IORQ Delay From Falling Edge of Clock

IORQ Low

–

– 85 ns

IORQ Delay From Rising Edge of Clock

IORQ High

tDHφ (IR)

–

– 85 ns

IORQ Delay From Falling Edge of Clock

IORQ High

–

– 85 ns

RD Delay From Rising Edge of Clock,

RD Low

tDLφ (RD) RD CL = 50pF

–

– 85 ns

RD Delay From Falling Edge of Clock,

RD Low

–

– 95 ns

RD Delay From Rising Edge of Clock,

RD High

tDHφ (RD)

–

– 85 ns

RD Delay From Falling Edge of Clock,

RD High

–

– 85 ns

WR Delay From Rising Edge of Clock,

WR Low

tDLφ (WR) WR CL = 50pF

–

– 65 ns

WR Delay From Falling Edge of Clock,

WR Low

–

– 80 ns

WR Delay From Falling Edge of Clock,

WR High

tDHφ (WR)

–

– 80 ns

Pulse Width, WR Low

tw (WRL)

Note 13 –

– ns

Note 8. tdcm = tc–170.

Note 9. tdci = tw (φL) + tr–170.

Note10. tcdf = tw (φL) + tr–70.

Note 11. tw (MRL) = tc–30.

Note12. tw (MRH) = tw (φH) + tr–20.

Note13. tw (WRL) = tc–30.

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