MSC8122(2006) 查看數據表（PDF） - Freescale Semiconductor

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MSC8122
(Rev.:2006)

Quad Core 16-Bit Digital Signal Processor

Freescale Semiconductor 

Signals/Connections

HD0/SWTE ↔ 1

HD1/DSISYNC ↔ 1

HD2/DSI64 ↔ 1 D

HD3/MODCK1 ↔ 1 S

HD4/MODCK2 ↔ 1

HD5/CNFGS ↔ 1

HD[6–31] ↔ 26

I

/

HD[32-39]/D[32-39]/reserved ↔ 8 S

HD40/D40/ETHRXD0 ↔ 1 Y

HD41/D41/ETHRXD1 ↔ 1 S.

HD42/D42/ETHRXD2/reserved ↔ 1 B

HD43/D43/ETHRXD3/reserved ↔ 1 U

HD[44-45]/D[44-45]/reserved ↔ 2 S

HD46/D46/ETHTXD0 ↔ 1 /

HD47/D47/ETHTXD1 ↔ 1 E

HD48/D48/ETHTXD2/reserved ↔ 1

HD49/D49/ETHTXD3/reserved ↔ 1

HD[50-53]/D[50-53]/reserved ↔ 4

HD54/D54/ETHTX_EN ↔ 1

T

H

E

HD55/D55/ETHTX_ER/reserved ↔ 1 R

HD56/D56/ETHRX_DV/ETHCRS_DV ↔ 1 N

HD57/D57/ETHRX_ER ↔ 1 E

HD58/D58/ETHMDC ↔ 1 T

HD59/D59/ETHMDIO ↔ 1

HD60/D60/ETHCOL/reserved ↔ 1

HD[61–63]/D[61-63]/reserved ↔ 3

HCID[0–2] → 3

HCID3/HA8 → 1 M

HA[11–29] → 19 E

HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3] → 4 M

HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/ ↔ 4 C

PWE[4–7]/PSDDQM[4–7]/PBS[4–7]

HRDS/HRW/HRDE → 1

HBRST → 1

HDST[0–1]/HA[9–10] → 2 D

HCS → 1 S

HBCS → 1 I

HTA ← 1

HCLKIN → 1

GPIO0/CHIP_ID0/IRQ4/ETHTXD0 ↔ 1

GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 ↔ 1 G

GPIO2/TIMER1/CHIP_ID2/IRQ6 ↔ 1 P

GPIO3/TDM3TSYN/IRQ1/ETHTXD2 ↔ 1 I

GPIO4/TDM3TCLK/IRQ2/ETHTX_ER ↔ 1 O

GPIO5/TDM3TDAT/IRQ3/ETHRXD3 ↔ 1

GPIO6/TDM3RSYN/IRQ4/ETHRXD2 ↔ 1

/

GPIO7/TDM3RCLK/IRQ5/ETHTXD3 ↔ 1 T

GPIO8/TDM3RDAT/IRQ6/ETHCOL ↔ 1 D

GPIO9/TDM2TSYN/IRQ7/ETHMDIO ↔ 1 M

GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC ↔ 1 /

GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD ↔ 1 E

GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC ↔ 1 T

GPIO13/TDM2RCLK/IRQ11/ETHMDC ↔ 1 H

GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC ↔ 1 E

GPIO15/TDM1TSYN/DREQ1 ↔ 1 R

GPIO16/TDM1TCLK/DONE1/DRACK1 ↔ 1 N

GPIO17/TDM1TDAT/DACK1 ↔ 1 E

GPIO18/TDM1RSYN/DREQ2 ↔ 1 T

GPIO19/TDM1RCLK/DACK2 ↔ 1

GPIO20/TDM1RDAT ↔ 1

GPIO21/TDM0TSYN ↔ 1

/

T

GPIO22/TDM0TCLK/DONE2/DRACK2 ↔ 1 I

GPIO23/TDM0TDAT/IRQ13 ↔ 1 M

GPIO24/TDM0RSYN/IRQ14 ↔ 1 E

GPIO25/TDM0RCLK/IRQ15 ↔ 1 R

GPIO26/TDM0RDAT ↔ 1 S

GPIO27/URXD/DREQ1 ↔ 1 /

GPIO28/UTXD/DREQ2 ↔ 1 I

GPIO29/CHIP_ID3/ETHTX_EN ↔ 1 2

GPIO30/TIMER2/TMCLK/SDA ↔ 1

GPIO31/TIMER3/SCL ↔ 1

C

32 ↔ A[0–31]

1 ↔ TT0/HA7

1 ↔ TT1

3 ↔ TT[2–4]/CS[5–7]

5 → CS[0–4]

4 ↔ TSZ[0–3]

1 ↔ TBST

1 ↔ IRQ1/GBL

1 ↔ IRQ3/BADDR31

1 ↔ IRQ2/BADDR30

1 ↔ IRQ5/BADDR29

1 → BADDR28

1 → BADDR27

1 ↔ BR

1 ↔ BG

S

Y

1 ↔ DBG

1 ↔ ABB/IRQ4

1 ↔ DBB/IRQ5

S 1 ↔ TS

T 1 ↔ AACK

E 1 ↔ ARTRY

M 32 ↔ D[0–31]

1 ↔ reserved/DP0/DREQ1/EXT_BR2

B 1 ↔ IRQ1/DP1/DACK1/EXT_BG2

U 1 ↔ IRQ2/DP2/DACK2/EXT_DBG2

S 1 ↔ IRQ3/DP3/DREQ2/EXT_BR3

1 ↔ IRQ4/DP4/DACK3/EXT_DBG3

1 ↔ IRQ5/DP5/DACK4/EXT_BG3

1 ↔ IRQ6/DP6/DREQ3

1 ↔ IRQ7/DP7/DREQ4

1 ↔ TA

1 ↔ TEA

1 ← NMI

1 → NMI_OUT

1 ↔ PSDVAL

1 ↔ IRQ7/INT_OUT

1 → BCTL0

M 1 → BCTL1/CS5

E 3 ↔ BM[0–2]/TC[0–2]/BNKSEL[0–2]

M 1 → ALE

C

4 → PWE[0–3]/PSDDQM[0–3]/PBS[0–3]

1 → PSDA10/PGPL0

1 → PSDWE/PGPL1

S 1 → POE/PSDRAS/PGPL2

Y 1 → PSDCAS/PGPL3

S 1 ↔ PGTA/PUPMWAIT/PGPL4/PPBS

1 → PSDAMUX/PGPL5

De 1 ← EE0

bug 1 → EE1

C 1 → CLKOUT

L 1 ← Reserved

K 1 ← CLKIN

R 1 ← PORESET

E 1 ↔ HRESET

S

E

1 ↔ SRESET

T 1 ← RSTCONF

J 1 ← TMS

T 1 ← TDI

A

G

1 ← TCK

1 ← TRST

1 → TDO

Ded. 1 ← ETHRX_CLK/ETHSYNC_IN

Eth. 1 ← ETHTX_CLK/ETHREF_CLK/ETHCLOCK

Net 1 ← ETHCRS/ETHRXD

Power signals are: VDD, VDDH, VCCSYN, GND, GNDH, and GNDSYN. Reserved signals can be left unconnected. NC signals must not be connected.

Figure 1-1. MSC8122 External Signals

MSC8122 Technical Data, Rev. 13

1-2

Freescale Semiconductor

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