MSC8122(2006) 查看數據表（PDF） - Freescale Semiconductor
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MSC8122 Datasheet PDF : 88 Pages
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Signals/Connections
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
TT1
TT[2–4]
Type
Description
Input/ Output
Bus Transfer Type 1
The bus master drives this pins during the address tenure to specify the type of the transaction. Some
applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101
and vice versa. In these applications, TT1 functions as read/write signal.
Input/ Output Bus Transfer Type 2–4
The bus master drives these pins during the address tenure to specify the type of the transaction.
CS[5–7]
CS[0–4]
TSZ[0–3]
TBST
IRQ1
GBL
IRQ3
BADDR31
IRQ2
BADDR30
IRQ5
BADDR29
BADDR28
BADDR27
Output
Chip Select 5–7
Enables specific memory devices or peripherals connected to the system bus.
Output
Chip Select 0–4
Enables specific memory devices or peripherals connected to the system bus.
Input/ Output Transfer Size 0–3
The bus master drives these pins with a value indicating the number of bytes transferred in the current
transaction.
Input/ Output Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers
eight words).
Input
Interrupt Request 11
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
Output
Input
Global1
When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin
indicates that the transfer is global and should be snooped by caches in the system.
Interrupt Request 31
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
Output
Input
Burst Address 311
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Interrupt Request 21
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
Output
Input
Burst Address 301
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Interrupt Request 51
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
Output
Output
Output
Bus Burst Address 291
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Burst Address 28
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
Burst Address 27
Five burst address output pins are outputs of the memory controller. These pins connect directly to
burstable memory devices without internal address incrementors controlled by the MSC8122 memory
controller.
1-10
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
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