Program
Sequencer
Address
Register
File
SC140
Core
Address
ALU
JTAG
EOnCE
Power
Management
Data ALU
Register
File
Data
ALU
Data Sheet Conventions
SC140 Core
64
Xa
64
Xb
128
P
Instruction
Cache
128
QBus
PIC
IRQs
LIC
QBus
Bank 1
M1
RAM
QBC
QBus
Bank 3
QBus
Interface
IRQs
MQBus
SQBus
128
128
Local Bus
64
Notes: 1. The arrows show the data transfer direction.
2. The QBus interface includes a bus switch, write buffer, fetch unit, and a
control unit that defines four QBus banks. In addition, the QBC handles internal
memory contentions.
Figure 2. SC140 Extended Core Block Diagram
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
iii