LTC1164-6C 查看數據表（PDF） - Linear Technology
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LTC1164-6C
Linear Technology
LTC1164-6C Datasheet PDF : 12 Pages
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LTC1164-6
PI FU CTIO S (14-Lead Dual-In-Line Package)
could go above ground, a signal diode must be used to
clamp V. Figures 1 and 2 show typical connections for dual
and single supply operation.
VIN
V+
0.1µF
1
14
2
13
3
12
4 LTC1164-6 11
5
10
6
9
7
8
V–
*
0.1µF
1k
CLOCK SOURCE
GND
+
DIGITAL SUPPLY
* OPTIONAL
VOUT
1164-6 F01
Figure 1. Dual Supply Operation for fCLK/fCUTOFF = 100:1
VIN
V+
10k
10k
1
14
2
13
0.1µF
3
12
4 LTC1164-6 11
5
10
6
9
7
8
1k
CLOCK SOURCE
GND
+
DIGITAL SUPPLY
+
1µF
VOUT
1164-6 F02
Figure 2. Single Supply Operation for fCLK/fCUTOFF = 100:1
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ±2.5V
Single Supply = 12V
Single Supply = 5V
HIGH LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
LOW LEVEL
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
V– (Pins 7, 14): Pins 7 and 14 should be connected
together. In a printed circuit board the connection should
be done under the IC package through a short trace
surrounded by the analog ground plane.
VOUT (Pins 9, 6): Pin 9 is the specified output of the filter;
it can typically source or sink 1mA. Driving coaxial cables
or resistive loads less than 20k will degrade the total
harmonic distortion of the filter. When evaluating the device’s
distortion an output buffer is required. A noninverting
buffer, Figure 3,can be used provided that its input common
mode range is well within the filter’s output swing. Pin 6 is
an intermediate filter output providing an unspecified 6th
order lowpass filter. Pin 6 should not be loaded.
ELLIPTIC/LINEAR PHASE (Pin 10): The DC level at this pin
selects the desired filter response, elliptic or linear phase
and determines the ratio of the clock frequency to the
cutoff frequency of the filter. Pin 10 connected to V –
provides an elliptic lowpass filter with clock-to-fCUTOFF
ratio of 100:1. Pin 10 connected to analog ground pro-
vides a linear phase lowpass filter with a clock- to-f–3dB
ratio of 160:1 and a transient response overshoot of 1%.
When Pin 10 is connected to V+ the clock-to-fCUTOFF ratio
is 50:1 and the filter response is elliptic. Bypassing Pin 10
to analog ground reduces the output DC offsets. If the DC
level at Pin 10 is switched mechanically or electrically at
slew rates greater than 1V/µs while the device is operating,
a 10k resistor should be connected between Pin 10 and the
DC source.
CLK (Pin 11): Any TTL or CMOS clock source with a
square-wave output and 50% duty cycle (±10%) is an
adequate clock source for the device. The power supply for
the clock source should not be the filter’s power supply.
The analog ground for the filter should be connected to
clock’s ground at a single point only. Table 1 shows the
clock’s low and high level threshold value for a dual or
single supply operation. A pulse generator can be used as
a clock source provided the high level ON time is greater
than 0.5µs. Sine waves are not recommended for clock
input frequencies less than 100kHz, since excessively
slow clock rise or fall times generate internal clock jitter
(maximum clock rise or fall time ≤ 1µs). The clock signal
should be routed from the right side of the IC package to
avoid coupling into any input or output analog signal path.
A 1k resistor between clock source and Pin 11 will slow
down the rise and fall times of the clock to further reduce
charge coupling, Figures 1 and 2.
–
1k
+
LT1006, fC < 5kHz
LT1200, fC > 5kHz
1164-6 F03
Figure 3. Buffer for Filter Output
11646fa
7
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