PI6C2516A 查看數據表（PDF） - Pericom Semiconductor Corporation
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PI6C2516A Datasheet PDF : 7 Pages
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PI6C2516
Phase-Locked Loop Clock Driver
with 16 Clock Outputs 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Pin Functions
Pin Name
Pin Number
Type
Description
CLK
12
I Clock input. CLK allows spread spectrum.
FB_IN
37
Feedback input. FB_IN provides the feedback signal to the internal PLL.
I CLK↑ and FB_IN↑ are synchronized so that there is normally zero phase
error between CLK and FB_IN.
Output bank enable. When 1G is LOW, outputs 1Y[0:3] are disabled to
1G
9
I a logic low state. When 1G is HIGH, all outputs 1Y[0:3] are enabled and
switched at the same frequency as CLK.
Output bank enable. When 2G is LOW, outputs 2Y[0:3] are disabled to
2G
16
I a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled and
switched at the same frequency as CLK.
Output bank enable. When 3G is LOW, outputs 3Y[0:3] are disabled to
3G
33
I a logic low state. When 3G is HIGH, all outputs 3Y[0:3] are enabled and
switched at the same frequency as CLK.
4G
FB_OUT
1Y[0:3]
40
35
2,3,6,7
Output bank enable. When 4G is LOW, outputs 4Y[0:3] are disabled to
I a logic low state. When 4G is HIGH, all outputs 4Y[0:3] are enabled and
switched at the same frequency as CLK.
O
Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an
embedded 25Ω series-damping resistor of the same value as the clock outputs.
Clock outputs. These outputs provide low-skew copies of CLK_IN.
O Each output has an embedded 25Ω series-damping resistor of the
same value as the clock outputs.
2Y[0:3]
18,19,22,23
Clock outputs. These outputs provide low-skew copies of CLK_IN.
O Each output has an embedded 25Ω series-damping resistor of the
same value as the clock outputs.
3Y[0:3]
4Y[0:3]
26,27,30,31
42,43,46,47
Clock outputs. These outputs provide low-skew copies of CLK_IN.
O Each output has an embedded 25Ω series-damping resistor of the
same value as the clock outputs.
Clock outputs. These outputs provide low-skew copies of CLK_IN.
O Each output has an embedded 25Ω series-damping resistor of the
same value as the clock outputs.
AVCC
11,38
Analog power supply. AVCC can be also used to bypass the PLL for
Power test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK
is buffered directly to the device outputs.
AGND
13,14,36
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
GND
1,8,17,24,25,32,41,48 Power Power supply
4,5,10,15,20,21,28,29,
34,39,44,45
Ground Ground
2
PS8440C 07/24/01
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