MPC5200BDS 查看數據表（PDF） - Freescale Semiconductor

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MPC5200BDS

SDRAM/DDR Memory Controller

Freescale Semiconductor 

1.2.1 System Oscillator Electrical Characteristics

Table 8. System Oscillator Electrical Characteristics

Characteristic

SYS_XTAL frequency

Oscillator start-up time

Sym

fsys_xtal

tup_osc

Notes Min Typical Max

15.6

33.3

35.0

—

—

10

Unit

MHz

ms

SpecID

O1.1

O1.2

1.2.2 RTC Oscillator Electrical Characteristics

Table 9. RTC Oscillator Electrical Characteristics

Characteristic

RTC_XTAL frequency

Sym

frtc_xtal

Notes Min Typical Max

—

32.768

—

Unit SpecID

kHz

O2.1

1.2.3 System PLL Electrical Characteristics

Table 10. System PLL Specifications

Characteristic

Sym

Notes Min Typical Max

Unit SpecID

SYS_XTAL frequency

SYS_XTAL cycle time

SYS_XTAL clock input jitter

fsys_xtal

tsys_xtal

tjitter

(1)

15.6

33.3

35.0

(1)

66.6

30.0

28.5

(2)

—

—

150

MHz

ns

ps

O3.1

O3.2

O3.3

System VCO frequency

System PLL relock time

fVCOsys

(1)

250

533

800

MHz

O3.4

tlock

(3)

—

—

100

μs

O3.5

1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU

(core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies.

2 This represents total input jitter—short term and long term combined—and is guaranteed by design. Two different

types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.

Systemic jitter is passed into and through the PLL to the internal clock circuitry.

3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required

for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

1.2.4 e300 Core PLL Electrical Characteristics

The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled

core PLL.

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

11

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