NT256S64V8HC0G 查看數據表（PDF） - Unspecified
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NT256S64V8HC0G Datasheet PDF : 10 Pages
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NT256S64V8HC0G
256MB : 32M x 64
Unbuffered SDRAM Module
AC Characteristics (TA =0 to 70 °C , VDD =3.3 ± 0.3V)
1. An initial pause of 200us,with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All Banks command must be given
followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.
2. The Transition time is measured between VIH and VIL (or between VIH and VIL ).
3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit between VIH and VIL (or between VIL
and VIH ) in a monotonic manner.
4. AC timing tests have VIL =0.8Vand VIH = 2.0 V with the timing referenced to the 1.40V crossover point.
5. AC measurements assume t T =1.2 ns.
AC Output Load Circuits
Clock
tCKL
tSETUP tHOLD
Input
Output
1.4V
tAC
tLZ
tT
tCKH
VIH
1.4V
VIL
tOH
1.4V
Output
Zo = 50 ohm
AC Output Load Circuit
50 pF
Preliminary 10 / 2001
7
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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