MAX8564A 查看數據表（PDF） - Maxim Integrated

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MAX8564A

±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers

Maxim Integrated 

±1%, Ultra-Low Output Voltage, Dual and Triple

Linear n-FET Controllers

Functional Diagram

VDD

GND

EN1

POK1

VL

VDD

VL

0.5V

REF

0.5V

UVLO

MAX8563

MAX8564

MAX8564A

VDD

GM

DRV1

EN2

POK2

EN3

POK3

POK

COMPARATOR

FB1

LDO

CONTROLLER 1

LDO

CONTROLLER 2

DRV2

FB2

LDO

CONTROLLER 3

DRV3

FB3

NAME

PIN

MAX8563

MAX8564/

MAX8564A

FUNCTION

Pin Description

Output n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 1.

1

DRV1

DRV1 DRV1 is internally pulled to ground when EN1 is logic low. Connect an external series RC circuit

for compensation. See the Stability Compensation section.

2

FB1

Feedback Input for Output 1. Connect to the center of a resistor-divider between output 1 and GND to

FB1

set the output voltage of output 1. The feedback regulation voltage is 0.500V. See the Output Voltage

Setting section.

3

EN1

EN1

Enable Control for Output 1. Drive logic high to enable output 1, or logic low to disable the

output. Connect to VDD for always-on operation.

4

POK1

POK1

Output 1 Power-Good Signal. Open-drain output pulls low when output 1 is 12% below the

nominal regulated voltage.

5

GND

GND Ground

6

—

POK2

Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the

nominal regulated voltage.

N.C.

—

No Internal Connection

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