LF9501JC25 查看數據表（PDF） - LOGIC Devices Incorporated

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LF9501JC25

Programmable Line Buffer

LOGIC Devices Incorporated 

DEVICES INCORPORATED

LF9501

Programmable Line Buffer

SIGNAL DEFINITIONS

Power

VCC and GND

+5 V power supply. All pins must be

connected.

Clock

CLK — Master Clock

The active edge of CLK, selected by

CLKSEL, strobes all registers. All

timing specifications are referenced to

the active edge of CLK.

Inputs

DI9-0 — Data Input

10-bit data, from the data input, is

latched into the device on the active

edge of CLK when MODSEL is LOW.

LC10-0 — Length Control Input

The 11-bit value is used to specify the

length of the delay buffer, between

DI9-0 and DO9-0, or the amount of

recirculation delay. An integer value

ranging from 0 to 1279 is used to

select a delay ranging from 2 to 1281

clock cycles. The value placed on the

LC10-0 inputs is equal to the desired

delay minus 2. The data presented on

LC10-0 is loaded into the device on the

active edge of CLK, selected by

CLKSEL, in conjunction with LCEN

being driven LOW.

Outputs

DO9-0 — Data Output

The 10-bit data output appears on

DO9-0 on the Nth clock cycle, where N

is the overall delay (desired delay).

Controls

LCEN — Length Control Enable

When LCEN is driven LOW, the next

active clock edge will cause the

loading of the delay value present at

the LC10-0 input.

OE — Output Enable

The Output Enable controls the state

of DO9-0. Driving OE LOW enables

the output port. When OE is HIGH,

DO9-0 is placed in a high-impedance

state. The internal transfer of data is

not affected by this control.

MODSEL — Mode Select

The Mode Select pin is used to choose

the desired mode of operation: data

delay mode or data recirculation

mode. Driving MODSEL LOW places

the device in the delay mode. The

device operates as a programmable

pipeline register. New data from the

DI9-0 input is loaded on every active

edge of CLK. Driving MODSEL

HIGH places the device in the data

recirculation mode. The device

operates as a programmable circular

buffer. The output of the device is

routed back to the input. MODSEL

may be changed during device

operation (synchronously), however,

the required setup and hold times,

with respect to CLK, must be met.

CLKSEL — Clock Select

The CLKSEL control allows the

selection of the active edge of CLK. A

LOW on CLKSEL selects negative-

edge triggering of the device. Driving

CLKSEL HIGH selects positive-edge

triggering. All timing specifications

are referrenced to the selected active

edge of CLK.

CLKEN — Clock Enable

The Clock Enable control enables and

disables the CLK input. Driving

CLKEN LOW enables CLK and causes

the device to operate in a normal

fashion. When CLKEN is HIGH, CLK

is disabled and the device will hold all

internal operations and data. CLKEN

may be changed during device

operation (synchronously), however,

the required setup and hold times,

with respect to CLK, must be met.

The changing of CLKEN takes effect

on the active edge of CLK following

the edge in which it was latched.

Video Imaging Products

2

08/16/2000–LDS.9501-H

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