74LVT16652ADL 查看數據表（PDF） - NXP Semiconductors.
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74LVT16652ADL Datasheet PDF : 22 Pages
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Philips Semiconductors
74LVT16652A
3.3 V 16-bit bus transceiver/register; 3-state
Table 3:
Symbol
VCC
1B1
1B0
GND
1SBA
1CPBA
1OEBA
Pin description …continued
Pin
Description
50
supply voltage
51
data input or output (B-side)
52
data input or output (B-side)
53
ground (0 V)
54
B to A select input
55
B to A clock input
56
B to A output enable input
7. Functional description
7.1 Function table
Table 4: Function table [1]
Operating mode
Input
nOEAB nOEBA nCPAB nCPBA nSAB
Isolation
L
H
H or L H or L X
Store A and B data
L
H
↑
↑
X
Store A, hold B
X
H
↑
H or L X
nSBA
X
X
X
Data I/O
nAx
input
input
input
Store A in both registers H
H
↑
↑
[3]
X
input
Hold A, store B
L
X
H or L ↑
X
X
unspecified
output [2]
Store B in both registers L
L
↑
↑
X
[3]
unspecified
output [2]
Real-time B data to A bus L
L
X
X
X
L
output
Store B data to A bus
L
L
X
H or L X
H
output
Real-time A data to B bus H
H
X
X
L
X
input
Store A data to B bus
H
H
H or L X
H
X
input
Stored A data to B bus and H
L
H or L H or L H
H
output
stored B data to A bus
nBx
input
input
unspecified
output [2]
unspecified
output [2]
input
input
input
input
output
output
output
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH clock transition.
[2] The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
[3] If both select controls (nSAB and nSBA) are LOW, then clocks can occur simultaneously. If either select control is HIGH, the clocks must
be staggered in order to load both registers.
9397 750 14402
Product data sheet
Rev. 03 — 12 January 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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