XRT83VSH316(2009) 查看數據表（PDF） - Exar Corporation

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XRT83VSH316
(Rev.:2009)

16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

REV. 1.0.1

RECEIVER SECTION

NAME

PIN

RCLK15

V12

RCLK14

R17

RCLK13

N18

RCLK12

V15

RCLK11

C15

RCLK10

H18

RCLK9

F17

RCLK8

C12

RCLK7

C9

RCLK6

F4

RCLK5

H3

RCLK4

C6

RCLK3

V6

RCLK2

N3

RCLK1

R4

RCLK0

V9

XRT83VSH316

16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

TYPE

O

DESCRIPTION

Receive Clock Output

RCLK is the recovered clock from the incoming data stream. If the incoming

signal is absent or RxON is pulled "Low", RCLK maintains its timing by using

an internal master clock as its reference. Software control (RCLKE) allows

RPOS/RNEG data to be updated on either edge of RCLK.

NOTE: RCLKE is a global setting that applies to all 16 channels.

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