IRMCF171
List of Figures
Figure 1. Typical Application Block Diagram Using IRMCF171 ................................................. 5
Figure 2. Pinout of IRMCF171 ................................................................................................... 6
Figure 3. IRMCF171 Block Diagram .......................................................................................... 7
Figure 4. IRMCF171 Leg Shunt Connection Diagram ............................................................... 9
Figure 5. IRMCF171 Single Shunt Connection Diagram ......................................................... 10
Figure 6. Crystal circuit example ............................................................................................. 17
Figure 7. Voltage droop and S/H hold time.............................................................................. 18
Figure 8 Op amp output capacitor ........................................................................................... 19
Figure 9. SYNC timing ............................................................................................................. 20
Figure 10. Gatekill timing ......................................................................................................... 21
Figure 11. ITRIP timing............................................................................................................ 21
Figure 12. Interrupt timing........................................................................................................ 22
Figure 13. I2C Timing ............................................................................................................... 23
Figure 14. SPI write timing....................................................................................................... 24
Figure 15. SPI read timing ....................................................................................................... 25
Figure 16. UART timing ........................................................................................................... 26
Figure 17. CAPTURE timing .................................................................................................... 27
Figure 18. JTAG timing............................................................................................................ 28
Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output............................. 29
Figure 20. All digital I/O except motor PWM output ................................................................. 29
Figure 21. RESET, GATEKILL I/O........................................................................................... 29
Figure 22. Analog input............................................................................................................ 30
Figure 24 Analog operational amplifier output and AREF I/O structure .................................. 30
Figure 25. VSS,AVSS pin I/O structure ................................................................................... 30
Figure 26. VDD1,VDDCAP pin I/O structure............................................................................ 31
Figure 27. XTAL0/XTAL1 pins structure .................................................................................. 31
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April 20, 2013