MF0ICU1 查看數據表（PDF） - NXP Semiconductors.

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MF0ICU1

MIFARE Ultralight contactless single-ticket IC

NXP Semiconductors. 

NXP Semiconductors

MF0ICU1

MIFARE Ultralight contactless single-ticket IC

7.2.4 Active state

In the active state either a 16-byte READ or 4-byte WRITE command can be performed.

The ACTIVE state is gratefully exited with the HLTA command and upon reception the

MF0ICU1 transits to the HALT state. Any other data received when the device is in this

state is interpreted as an error. Depending on its previous state the MF0ICU1 returns to

either the IDLE state or HALT state.

7.2.5 Halt state

The HALT and IDLE states constitute the two wait states implemented in the MF0ICU1.

An already processed MF0ICU1 can be set into the HALT state using the HLTA command.

In the anticollision phase, this state helps the PCD to distinguish between processed

cards and cards yet to be selected. The MF0ICU1 can only exit this state on execution of

the WUPA command. Any other data received when the device is in this state is

interpreted as an error and the MF0ICU1 state remains unchanged. Refer to Ref. 3 for

correct implementation of an anticollision procedure based on the IDLE and HALT states

and the REQA and WUPA commands.

7.3 Data integrity

Reliable data transmission is ensured over the contactless communication link between

PCD and MF0ICU1 as follows:

• 16-bit CRC for each block

• Parity bits for each byte

• Bit count checking

• Bit coding to distinguish between logic 1, logic 0 and no information

• Channel monitoring (protocol sequence and bit stream analysis)

7.4 RF interface

The RF interface is based on the ISO/IEC 14443 A standard for contactless smart cards.

The RF field from the PCD is always present as it is used for the card power supply.

However, it is sequentially interrupted during data transmission to allow the data to be

sent. There is only one start bit at the beginning of each frame for data communication

irrespective of direction. Each byte is transmitted with an odd parity bit at the end of the

byte. The LSB of the byte with the lowest selected block address is transmitted first. The

maximum frame length is 163-bit:

(16 data bytes + 2 CRC bytes = 16 * 9 + 2 * 9 + 1 start bit = 163).

028639

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.9 — 23 July 2014

028639

© NXP Semiconductors N.V. 2014. All rights reserved.

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