AR9341 查看數據表（PDF） - Unspecified

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AR9341

Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4 GHz Premium SoC for Advanced WLAN Platforms

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PRELIMINARY

185

8.9.7 SLIC Rx Slots 2 (SLIC_RX_SLOTS2)

185

8.9.8 SLIC Timing Control

(SLIC_TIMING_CTRL) ............ 186

8.9.9 SLIC Interrupt (SLIC_INTR) ... 187

8.9.10 SLIC Swap (SLIC_SWAP) ....... 187

8.10 Stereo Registers ................................... 188

8.10.1 Configure Stereo Block

(STEREO_CONFIG) ................. 188

8.10.2 Set Stereo Volume

(STEREO_VOLUME) ............... 190

8.10.3 Stereo Master Clock

(STEREO_MASTER_CLOCK) 191

8.10.4 Tx Sample Counter

(STEREO_TX_SAMPLE_CNT_LSB)

..................................................... 191

8.10.5 Tx Sample Counter

(STEREO_TX_SAMPLE_CNT_MSB

) .................................................... 191

8.10.6 Rx Sample Counter

(STEREO_RX_SAMPLE_CNT_LSB)

..................................................... 191

8.10.7 Rx Sample Counter

(STEREO_RX_SAMPLE_CNT_MSB

) .................................................... 191

8.11 WDMA Registers ................................ 192

8.11.1 Command (CR) ......................... 193

8.11.2 Configuration and Status (CFG) ...

193

8.11.3 Rx DMA Data Buffer Pointer

Threshold (RXBUFPTR_THRESH)

194

8.11.4 Tx DMA Descriptor Pointer

Threshold (TXDPPTR_THRESH) .

194

8.11.5 Maximum Interrupt Rate Threshold

(MIRT) ........................................ 194

8.11.6 Interrupt Global Enable (IER) . 195

8.11.7 Tx Interrupt Mitigation Thresholds

(TIMT) ........................................ 195

8.11.8 Rx Interrupt Mitigation Thresholds

(RIMT) ........................................ 195

8.11.9 Tx Configuration (TXCFG) ...... 196

8.11.10 Rx Configuration (RXCFG) ... 196

8.11.11 MIB Control (MIBC) ............... 197

8.11.12 Global Tx Timeout (GTT) ...... 197

8.11.13 Global Tx Timeout Mode (GTTM)

197

8.11.14 Carrier Sense Timeout (CST) 198

8.11.15 Size of High and Low Priority

(RXDP_SIZE) ............................. 198

8.11.16 MAC Rx High Priority Queue

RXDP Pointer

(RX_QUEUE_HP_RXDP) ........ 198

8.11.17 MAC Rx Low Priority Queue

RXDP Pointer

(RX_QUEUE_LP_RXDP) ......... 198

8.11.18 Primary Interrupt Status (ISR_P)

199

8.11.19 Secondary Interrupt Status 0

(ISR_S0) ...................................... 200

8.11.20 Secondary Interrupt Status 1

(ISR_S1) ...................................... 200

8.11.21 Secondary Interrupt Status 2

(ISR_S2) ...................................... 201

8.11.22 Secondary Interrupt Status 3

(ISR_S3) ...................................... 202

8.11.23 Secondary Interrupt Status 4

(ISR_S4) ...................................... 202

8.11.24 Secondary Interrupt Status 5

(ISR_S5) ...................................... 202

8.11.25 Primary Interrupt Mask (IMR_P)

8.11.26 Secondary Interrupt Mask 0

(IMR_S0) .................................... 204

8.11.27 Secondary Interrupt Mask 1

(IMR_S1) .................................... 204

8.11.28 Secondary Interrupt Mask 2

(IMR_S2) .................................... 205

8.11.29 Secondary Interrupt Mask 3

(IMR_S3) .................................... 205

8.11.30 Secondary Interrupt Mask 4

(IMR_S4) .................................... 206

8.11.31 Secondary Interrupt Mask 5

(IMR_S5) .................................... 206

8.11.32 Primary Interrupt Status Read and

Clear (ISR_P_RAC) ................... 206

8.11.33 Secondary Interrupt Status 0

(ISR_S0_S) .................................. 207

8.11.34 Secondary Interrupt Status 1

(ISR_S1_S) .................................. 207

8.11.35 Secondary Interrupt Status 2

(ISR_S2_S) .................................. 207

8.11.36 Secondary Interrupt Status 3

8 • AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz SoC Atheros Communications, Inc.

8 • April 2011

COMPANY CONFIDENTIAL

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