AR9341 查看數據表（PDF） - Unspecified

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AR9341

Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4 GHz Premium SoC for Advanced WLAN Platforms

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PRELIMINARY

(ISR_S3_S) .................................. 207

8.11.37 Secondary Interrupt Status 4

(ISR_S4_S) .................................. 207

8.11.38 Secondary Interrupt Status 5

(ISR_S5_S) .................................. 207

8.12 WQCU Registers ................................. 208

8.12.1 Tx Queue Descriptor (Q_TXDP) ...

208

8.12.2

QCU_STATUS_RING_START_AD

DRESS Lower 32 bits of Address

(Q_STATUS_RING_START) ... 209

8.12.3

QCU_STATUS_RING_END_ADD

R Lower 32 Bits of Address

(Q_STATUS_RING_END) ....... 209

8.12.4 QCU_STATUS_RING_CURRENT

Address

(Q_STATUS_RING_CURRENT) ..

209

8.12.5 Tx Queue Enable (Q_TXE) ...... 209

8.12.6 Tx Queue Disable (Q_TXD) .... 210

8.12.7 CBR Configuration (Q_CBRCFG)

210

8.12.8 ReadyTime Configuration

(Q_RDYTIMECFG) ................... 210

8.12.9 OneShotArm Set Control

(Q_ONESHOTARM_SC) ......... 211

8.12.10 OneShotArm Clear Control

(Q_ONESHOTARM_CC) ........ 211

8.12.11 Misc. QCU Settings (Q_MISC) 212

8.12.12 Misc. QCU Status (Q_STS) ..... 214

8.12.13 ReadyTimeShutdown Status

(Q_RDYTIMESHDN) ............... 214

8.12.14 Descriptor CRC Check

(MAC_QCU_DESC_CRC_CHK) ..

214

8.13 WLAN DCU Registers ....................... 215

8.13.1 QCU Mask (D_QCUMASK) .... 215

8.13.2 DCU-Specific IFS Settings

(D_LCL_IFS) .............................. 216

8.13.3 Retry Limits (D_RETRY_LIMIT) ..

216

8.13.4 ChannelTime Settings

(D_CHNTIME) .......................... 216

8.13.5 Misc. DCU-Specific Settings

(D_MISC) ................................... 217

8.13.6 DCU-Global IFS Settings: SIFS

Duration (D_GBL_IFS_SIFS) ... 217

8.13.7 DCU-Global IFS Settings: Slot

Duration (D_GBL_IFS_SLOT) 217

8.13.8 DCU-Global IFS Settings: EIFS

Duration (D_GBL_IFS_EIFS) .. 218

8.13.9 DCU-Global IFS Settings: Misc.

Parameters (D_GBL_IFS_MISC) ..

218

8.13.10 DCU Tx Pause Control/Status

(D_TXPSE) ................................. 219

8.13.11 DCU Transmission Slot Mask

(D_TXSLOTMASK) .................. 219

8.14 WMAC Glue Registers ....................... 220

8.14.1 Interface Reset Control

(WMAC_GLUE_INTF_RESET_CO

NTROL) ..................................... 221

8.14.2 Power Management Control

(WMAC_GLUE_INTF_PM_CTRL)

8.14.3 AXI Timeout Counter for DMA

(WMAC_GLUE_INTF_TIMEOUT)

8.14.4 Synchronous Interrupt Cause

(WMAC_GLUE_INTF_INTR_SYN

C_CAUSE) ................................. 221

8.14.5 Synchronous Interrupt Enable

(WMAC_GLUE_INTF_INTR_SYN

C_ENABLE) .............................. 222

8.14.6 Asynchronous Interrupt Mask

(WMAC_GLUE_INTF_INTR_ASY

NC_MASK) ............................... 222

8.14.7 Synchronous Interrupt Mask

(WMAC_GLUE_INTF_INTR_SYN

C_MASK) ................................... 222

8.14.8 Asynchronous Interrupt Mask

(WMAC_GLUE_INTF_INTR_ASY

NC_CAUSE) .............................. 222

8.14.9 Asynchronous Interrupt Enable

(WMAC_GLUE_INTF_INTR_ASY

NC_ENABLE) ........................... 222

8.14.10 GPIO Input

(WMAC_GLUE_INTF_GPIO_IN)

223

8.14.11 WMAC Glue GPIO Input Value

(WMAC_GLUE_INTF_GPIO_INP

UT_VALUE) .............................. 223

8.14.12 Output Values from MAC to GPIO

Pins

Atheros Communications, Inc.

SoC • 9

AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz

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