AR9341 查看數據表（PDF） - Unspecified

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AR9341

Highly-Integrated and Feature-Rich IEEE 802.11n 2x2 2.4 GHz Premium SoC for Advanced WLAN Platforms

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PRELIMINARY

8.7.108 Ingress ACL Rule Table2 Upper

(IG_ACL_RULE_TABLE2_UPPER)

172

8.7.109 Ingress ACL Rule Table3 Lower

(IG_ACL_RULE_TABLE3_LOWER

) .................................................... 172

8.7.110 Ingress ACL Rule Table3 Upper

(IG_ACL_RULE_TABLE3_UPPER)

172

8.7.111 Egress ACL Rule Table0 Lower

(EG_ACL_RULE_TABLE0_LOWE

R) ................................................. 172

8.7.112 Egress ACL Rule Table0 Upper

(EG_ACL_RULE_TABLE0_UPPER)

..................................................... 172

8.7.113 Egress ACL Rule Table1 Lower

(EG_ACL_RULE_TABLE1_LOWE

R) ................................................. 173

8.7.114 Egress ACL Rule Table1 Upper

(EG_ACL_RULE_TABLE1_UPPER)

..................................................... 173

8.7.115 Egress ACL Rule Table2 Lower

(EG_ACL_RULE_TABLE2_LOWE

R) ................................................. 173

8.7.116 Egress ACL Rule Table2 Upper

(EG_ACL_RULE_TABLE2_UPPER)

..................................................... 173

8.7.117 Egress ACL Rule Table3 Lower

(EG_ACL_RULE_TABLE3_LOWE

R) ................................................. 173

8.7.118 Egress ACL Rule Table3 Upper

(EG_ACL_RULE_TABLE3_UPPER)

..................................................... 173

8.8 MBOX Registers ................................... 174

8.8.1 Non-Destructive FIFO Status Query

(MBOX_FIFO_STATUS) .......... 174

8.8.2 Non-Destructive SLIC FIFO Status

Query

(SLIC_MBOX_FIFO_STATUS) 175

8.8.3 Mailbox DMA Engine Policy

Control (MBOX_DMA_POLICY) .

175

8.8.4 SLIC Mailbox DMA Engine Policy

Control

(SLIC_MBOX_DMA_POLICY) 176

8.8.5 Rx DMA Descriptors Base Address

(MBOX_DMA_RX_DESCRIPTOR_

BASE) .......................................... 176

8.8.6 Rx DMA Control

(MBOX_DMA_RX_CONTROL) 177

8.8.7 Tx DMA Descriptors Base Address

(MBOX_DMA_TX_DESCRIPTOR_

BASE) ......................................... 177

8.8.8 Tx DMA Control

(MBOX_DMA_TX_CONTROL) 178

8.8.9 SLIC Rx DMA Descriptors Base

Address

(SLIC_DMA_RX_DESCRIPTOR_B

ASE) ............................................ 178

8.8.10 SLIC Rx DMA Control

(SLIC_DMA_RX_CONTROL) 179

8.8.11 SLIC Tx DMA Descriptors Base

(SLIC_DMA_TX_DESCRIPTOR_B

ASE) ............................................ 179

8.8.12 SLIC Tx DMA Control

(SLIC_DMA_TX_CONTROL) 180

8.8.13 Mailbox FIFO Status

(MBOX_FRAME) ...................... 180

8.8.14 SLIC Mailbox FIFO Status

(SLIC_MBOX_FRAME) ........... 180

8.8.15 FIFO Timeout Period

(FIFO_TIMEOUT) .................... 181

8.8.16 MBOX Related Interrupt Status

(MBOX_INT_STATUS) ............ 181

8.8.17 SLIC MBOX Related Interrupt

(SLIC_MBOX_INT_STATUS) . 182

8.8.18 MBOX Related Interrupt Enables

(MBOX_INT_ENABLE) ........... 182

8.8.19 SLIC MBOX Related Interrupt

(SLIC_MBOX_INT_ENABLE) 183

8.8.20 Reset and Clear MBOX FIFOs

(MBOX_FIFO_RESET) ............. 183

8.8.21 SLIC Reset and Clear MBOX FIFOs

(SLIC_MBOX_FIFO_RESET) .. 183

8.9 SLIC Registers ...................................... 184

8.9.1 SLIC Slots (SLIC_SLOT) .......... 184

8.9.2 SLIC Clock Control

(SLIC_CLOCK_CONTROL) ... 184

8.9.3 SLIC Control (SLIC_CTRL) ..... 185

8.9.4 SLIC Tx Slots 1 (SLIC_TX_SLOTS1)

185

8.9.5 SLIC Tx Slots 2 (SLIC_TX_SLOTS2)

185

8.9.6 SLIC Rx Slots 1 (SLIC_RX_SLOTS1)

Atheros Communications, Inc.

SoC • 7

AR9341 Highly-Integrated and Feature-Rich 802.11n 2x2 2.4 GHz

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