AN28F010-150 查看數據表（PDF） - Intel
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AN28F010-150 Datasheet PDF : 23 Pages
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A28F010
Bus
Operation
Command
Comments
Entire Memory Must e 00H
Before Erasure
Standby
Use Quick-Pulse
Programming Algorithm
(Figure 4)
Wait for VPP Ramp to VPPH(1)
Write
Write
Set-up
Erase
Erase
Initialize Addresses and
Pulse-Count
Data e 20H
Data e 20H
Standby
Write
Standby
Read
Erase(3)
Verify
Duration of Erase Operation
(tWHWH2)
Addr e Byte to Verify
Data e A0H Stops Erase
Operation(2)
tWHGL
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Write
Read
Standby
Data e 00H Resets the
Register for Read Operations
Wait for VPP Ramp to VPPL(1)
290266 – 6
NOTES
1 See DC Characteristics for value of VPPH The VPP
power supply can be hard-wired to the device or
switchable When VPP is switched VPPL may be
ground no-connect with a resistor tied to ground or
less than 6 5V Refer to Principles of Operation
2 Refer to Principles of Operation
3 Erase Verify is performed only after chip-erasure A
final read compare may be performed (optional) after
the register is written with the read command
4 CAUTION The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice
Figure 5 A28F010 Quick-Erase Algorithm
11
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