TE28F010-150 查看數據表（PDF） - Intel
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TE28F010-150 Datasheet PDF : 33 Pages
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E
28F010
Table 2. 28F010 Bus Operations
Mode
VPP(1) A0
A9 CE# OE# WE# DQ0–DQ7
Read
VPPL A0
A9
VIL VIL VIH Data Out
Output Disable
VPPL X
X
VIL VIH VIH Tri-State
READ-ONLY Standby
VPPL X
X VIH X X Tri-State
Intelligent Identifier (Mfr)(2)
VPPL VIL VID(3) VIL VIL VIH Data = 89H
Intelligent Identifier (Device)(2) VPPL VIH VID(3) VIL VIL VIH Data = B4H
Read
VPPH A0
A9
VIL VIL VIH Data Out(4)
READ/WRITE Output Disable
VPPH X
X
VIL VIH VIH Tri-State
Standby(5)
VPPH X
X VIH X X Tri-State
Write
VPPH A0
A9
VIL VIH VIL Data In(6)
NOTES:
1. Refer to DC Characteristics. When VPP = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
4. Read operations with VPP = VPPH may access array data or the intelligent identifier codes.
5. With VPP at high voltage, the standby current equals ICC + IPP (standby).
6. Refer to Table 3 for valid data-in during a write operation.
7. X can be VIL or VIH.
2.2 Write Protection
The command register is only active when VPP is at
high voltage. Depending upon the application, the
system designer may choose to make the VPP
power supply switchable—available only when
memory updates are desired. When VPP = VPPL, the
contents of the register default to the Read
command, making the 28F010 a read-only memory.
In this mode, the memory contents cannot be
altered.
Or, the system designer may choose to “hardwire”
VPP, making the high voltage supply constantly
available. In this case, all command register
functions are inhibited whenever VCC is below the
write lockout voltage VLKO. (See Section 3.4,
Power-Up/Down Protection.) The 28F010 is
designed to accommodate either design practice,
and to encourage optimization of the processor
memory interface.
The two-step program/erase write sequence to the
command register provides additional software
write protections.
2.2.1
BUS OPERATIONS
2.2.1.1
Read
The 28F010 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins, independent
of device selection. Refer to the AC read timing
waveforms.
When VPP is high (VPPH), the read operation can be
used to access array data, to output the intelligent
identifier codes, and to access data for
program/erase verification. When VPP is low (VPPL),
the read operation can only access the array data.
2.2.1.2
Output Disable
With OE# at a logic-high level (VIH), output from the
device is disabled. Output pins are placed in a high-
impedance state.
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