NTE21128 查看數據表（PDF） - NTE Electronics
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NTE21128 Datasheet PDF : 6 Pages
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Device Operation (Cont’d):
Two Line Output Control
The NTE21128 features a 2 line control function which accommodates the use of multiple memory
connection. The two line control function allows:
a.
the lowest possible memory power dissipation,
b.
complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary
device selecting function, while G should be made a common connection to all devices in the array
and connected to the READ line from the system control bus.
This ensures that all deselected memory devices are in their low power standby mode and that the
output pins are only active when data is required from a particular memory device.
System Considerations
The power switching characteristics of EPROMs require careful decoupling of the devices. The sup-
ply current (ICC) has three segments that are of interest to the system designer: the standby current
level, the active current level, and transient current peaks that are produced by the falling and rising
edges of E. The magnitude of these transient current peaks is dependent on the capacitive and induc-
tive loading of the device at the output. The associated transient voltage peaks can be suppressed
by complying with the two line output control and by properly selecting decoupling capacitors. It is
recommended that a 1µf ceramic capacitor be used on every device between VCC and VSS. This
should be a high frequency capacitor of low inherent inductance and should be placed as close to the
device as possible. In addition, a 4.7µf bulk electrolytic capacitor should be used between VCC and
GND for every eight devices. The bulk capacitor should be located near the power supply connection
point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive ef-
fects of PCB traces.
Programming
When delivered, all bits of the NTE21128 are in the “1” state. Data is introduced by selectively pro-
gramming “0s” into the desired bit locations. Although only “0s” will be programmed, both “1s” and
“0s” can be present in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure.
The NTE21128 is in the programming mode when the VPP input is at 12.5V and E and P are at TTL
low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required
for the address and data inputs are TTL.
Fast Programming Algorithm
Fast Programming Algorithm rapidly programs the NTE21128 EPROM using an efficient and reliable
method suited to the production programming environment. Programming reliability is also ensured
as the incremental program margin of each byte is continually monitored to determine when it has
been successfully programmed. The Fast Programming Algorithm utilizes two different pulse types:
initial and overprogram.
The duration of the initial P pulse(s) is 1ms, which will then be followed by a longer overprogram pulse
of length 3ms by n (n is equal to the number of the initial one–millisecond pulses applied to a particular
NTE21128 location), before a correct verify occurs. Up to 25 one–millisecond pulses per byte are
provided for before the over program pulse is applied.
The entire sequence of program pulses and byte verifications is performed at VCC = 6V and VPP =
12.5V. When the Fast Programming cycle has been completed, all bytes should be compared to the
original data with VCC = 5V and VPP = 5V.
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