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CAT24AA16(2018) 查看數據表(PDF) - ON Semiconductor

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CAT24AA16
(Rev.:2018)
ON-Semiconductor
ON Semiconductor ON-Semiconductor
CAT24AA16 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
CAT24AA16
READ OPERATIONS
Immediate Read
sequence by sending data, the Master then creates a START
To read data from memory, the Master creates a START condition and broadcasts a Slave address with the R/W bit
condition on the bus and then broadcasts a Slave address set to ‘1’. The Slave responds with ACK after every byte sent
with the R/W bit set to ‘1’. The Slave responds with ACK by the Master and then sends out data residing at the selected
and starts shifting out data residing at the current address. address. After receiving the data, the Master responds with
After receiving the data, the Master responds with NoACK NoACK and then terminates the session by creating a STOP
and terminates the session by creating a STOP condition on condition on the bus (Figure 11).
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
Selective Read
If, after receiving data sent by the Slave, the Master
To read data residing at a specic address, the selected responds with ACK, then the Slave will continue
address must rst be loaded into the internal address register. transmitting until the Master responds with NoACK
This is done by starting a Byte Write sequence, whereby the followed by STOP (Figure 12). During Sequential Read the
Master creates a START condition, then broadcasts a Slave internal byte address is automatically incremented up to the
address with the R/W bit set to ‘0’ and then sends an address end of memory, where it then wraps around to the beginning
byte to the Slave. Rather than completing the Byte Write of memory.
N
S
O
BUS ACTIVITY: T
S
A
MASTER R
SLAVE
ADDRESS
AT
CO
T
KP
S
P
SLAVE
A
C
K
DATA
BYTE
SCL
8
9
SDA
8th Bit
DATA OUT
NO ACK
Figure 10. Immediate Read Sequence and Timing
S
BUS ACTIVITY: T
A
MASTER R
T
SLAVE
ADDRESS
ADDRESS
BYTE
S
T
A
R
SLAVE
ADDRESS
T
S
S
SLAVE
A
A
A
C
C
C
K
K
K
BUS ACTIVITY:
SLAVE
MASTER ADDRESS
Figure 11. Selective Read Sequence
A
A
A
C
C
C
K
K
K
SLAVE
A
C
DATA
K
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
Figure 12. Sequential Read Sequence
STOP
N
O
S
AT
CO
KP
P
DATA
BYTE
N
O
S
AT
CO
KP
P
DATA
BYTE
n+x
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