CXD3521GG 查看數據表（PDF） - Sony Semiconductor

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CXD3521GG

Interface and Driver IC for LCD

Sony Semiconductor 

CXD3521GG

AC Characteristics

Item

Symbol

HCK/HST time

difference

t∆ HST-HCKU

t∆ HST-HCKD

Data output

rise time

tRD

Data output

fall time

tFD

(VDD = 3.0 to 3.6V, Ta = –25 to +75°C)

Applicable pins

Conditions∗1 Min.

Typ.

Max. Unit

HCK1, HCK2, XHCK1,

XHCK2, HST1, HST2,

—

XHST1, XHST2

—

—

15∗2 ns

R01, R11, R21, R31,

R02, R12, R22, R32,

XR01, XR11, XR21, XR31, GND – VDD

XR02, XR12, XR22, XR32, (0 – 90%)

—

—

35

G01, G11, G21, G31,

G02, G12, G22, G32,

XG01, XG11, XG21, XG31,

ns

XG02, XG12, XG22, XG32,

B01, B11, B21, B31,

B02, B12, B22, B32,

VDD – GND

(100 – 10%)

—

—

35

XB01, XB11, XB21, XB31,

XB02, XB12, XB22, XB32

Horizontal pulse

output rise time

tRHP

Horizontal pulse

output fall time

tFHP

HCK1, HCK2,

XHCK1, XHCK2,

HST1, HST2,

XHST1, XHST2

GND – VDD

(0 – 90%)

—

—

35

ns

VDD – GND

(100 – 10%)

—

—

35

Vertical pulse

output rise time

tRVP

VCK, XVCK, VST, XVST, GND – VDD

ENB, XENB, OE1, OE2, (0 – 90%)

—

—

50

Vertical pulse

output fall time

tFVP

XOE1, XOE2, PCO,

TESTO

VDD – GND

(100 – 10%)

—

—

ns

50

HCK1, HCK2,

XHCK1, XHCK2/ tSTP

DATA setup time

HCK1, HCK2,

XHCK1, XHCK2,

R01, R11, R21, R31,

R02, R12, R22, R32,

XR01, XR11, XR21, XR31,

XR02, XR12, XR22, XR32,

G01, G11, G21, G31,

∗3

G02, G12, G22, G32,

XG01, XG11, XG21, XG31,

XG02, XG12, XG22, XG32,

B01, B11, B21, B31,

B02, B12, B22, B32,

XB01, XB11, XB21, XB31,

XB02, XB12, XB22, XB32

35

55

100 ns

HCK, VCK duty

dHCK

dVCK

HCK1, HCK2, XHCK1, ∗4

XHCK2, VCK, XVCK

48

50

52

%

∗1 Load capacitance CL of each output pin is shown below.

• R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01,

G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01,

B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, OE1, XOE1,

OE2, XOE2, TESTO, ENB, XENB

: CL = 70pF

• HCK1, HCK2, XHCK1, XHCK2

: CL = 180pF

• VCK, XVCK

: CL = 150pF

• HST1, HST2, XHST1, XHST2, VST, XVST, PCO : CL = 100pF

∗2 Absolute value of the time difference of the change point at HST1, XHST1, HCK1 and XHCK1 (50%) is

within 15ns.

Similarly, absolute value of the time difference of the change point at HST2, XHST2, HCK2 and XHCK2

(50%) is within 15ns.

∗3 tSTP: tST1D, tST1U, tST2D, tST2U

∗4 dHCK = (tHH/(tHH + tHL)) × 100, dVCK = (tVH/(tVH + tVL)) × 100

–9–

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