73S1210F-IM68EB 查看數據表（PDF） - Teridian Semiconductor Corporation

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73S1210F-IM68EB

Self-Contained Smart Card Reader with PINpad and Power Management

Teridian Semiconductor Corporation 

DS_1210F_001

73S1210F Data Sheet

Tables

Table 1: 73S1210 Pinout Description ........................................................................................................... 8

Table 2: MPU Data Memory Map ............................................................................................................... 11

Table 3: Flash Special Function Registers ................................................................................................. 13

Table 4: Internal Data Memory Map ........................................................................................................... 14

Table 5: Program Security Registers .......................................................................................................... 17

Table 6: IRAM Special Function Registers Locations ................................................................................ 18

Table 7: IRAM Special Function Registers Reset Values .......................................................................... 19

Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20

Table 9: PSW Register................................................................................................................................ 21

Table 10: Port Registers ............................................................................................................................. 21

Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 23

Table 12: The MCLKCtl Register ................................................................................................................ 23

Table 13: The TCON Register .................................................................................................................... 24

Table 14: The INT5Ctl Register .................................................................................................................. 30

Table 15: The MISCtl0 Register.................................................................................................................. 30

Table 16: The MISCtl1 Register.................................................................................................................. 31

Table 17: The MCLKCtl Register ................................................................................................................ 31

Table 18: The PCON Register .................................................................................................................... 32

Table 19: The IEN0 Register ...................................................................................................................... 34

Table 20: The IEN1 Register ...................................................................................................................... 35

Table 21: The IEN2 Register ...................................................................................................................... 35

Table 22: The TCON Register .................................................................................................................... 36

Table 23: The T2CON Register .................................................................................................................. 36

Table 24: The IRCON Register................................................................................................................... 37

Table 25: External MPU Interrupts.............................................................................................................. 37

Table 26: Control Bits for External Interrupts.............................................................................................. 38

Table 27: Priority Level Groups .................................................................................................................. 38

Table 28: The IP0 Register ......................................................................................................................... 38

Table 29: The IP1 Register ......................................................................................................................... 39

Table 30: Priority Levels.............................................................................................................................. 39

Table 31: Interrupt Polling Sequence.......................................................................................................... 39

Table 32: Interrupt Vectors ......................................................................................................................... 39

Table 33: UART Modes .............................................................................................................................. 40

Table 34: Baud Rate Generation ................................................................................................................ 40

Table 35: The PCON Register .................................................................................................................... 41

Table 36: The BRCON Register ................................................................................................................. 41

Table 37: The MISCtl0 Register.................................................................................................................. 42

Table 38: The S0CON Register .................................................................................................................. 43

Table 39: The S1CON Register .................................................................................................................. 44

Table 40: The TMOD Register .................................................................................................................... 45

Table 41: Timers/Counters Mode Description ............................................................................................ 45

Table 42: The TCON Register .................................................................................................................... 46

Table 43: The IEN0 Register ...................................................................................................................... 47

Table 44: The IEN1 Register ...................................................................................................................... 48

Table 45: The IP0 Register ......................................................................................................................... 48

Table 46: The WDTREL Register ............................................................................................................... 48

Table 47: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49

Table 48: UDIR Control Bit ......................................................................................................................... 49

Table 49: Selectable Controls Using the UxIS Bits..................................................................................... 49

Table 50: The USRIntCtl1 Register ............................................................................................................ 50

Table 51: The USRIntCtl2 Register ............................................................................................................ 50

Table 52: The USRIntCtl3 Register ............................................................................................................ 50

Table 53: The USRIntCtl4 Register ............................................................................................................ 50

Table 54: The ACOMP Register ................................................................................................................. 51

Table 55: The INT6Ctl Register .................................................................................................................. 52

Table 56: The LEDCtl Register ................................................................................................................... 53

Rev. 1.4

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