EFM32LG360F64G-E-CSP81 查看數據表（PDF） - Unspecified
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EFM32LG360F64G-E-CSP81 Datasheet PDF : 466 Pages
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3. System Summary
EFM32LG Data Sheet
System Summary
3.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the
EFM32LG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of
the configuration for the EFM32LG devices. For a complete feature set and in-depth information on the modules, the reader is referred
to the EFM32LG Reference Manual.
A block diagram of the EFM32LG is shown in the following figure.
Core / Memory
ARM CortexTM
M3 processor
Memory
Protection Unit
Flash Program
Memory
RAM Memory
Debug w/ ETM
DMA Controller
Clock Management
High Frequency
Crystal Oscillator
High Frequency
RC Oscillator
Auxiliary High
Freq. RC Osc.
Low Freq.
RC Oscillator
Low Frequency
Crystal Oscillator
Ultra Low Freq.
RC Oscillator
Energy Management
Voltage
Regulator
Voltage
Comparator
Brown-out
Detector
Power-on
Reset
Back-up Power
Domain
Security
Hardware AES
Serial Interfaces
USART
UART
Low Energy
UARTTM
I2C
USB
32-bit bus
Peripheral Reflex System
I/O Ports
Timers and Triggers
External Bus
Interface
External
Interrupts
Pin Reset
TFT Driver
General
Purpose I/O
Pin Wakeup
Timer/Counter
LESENSE
Low Energy Timer Real Time Counter
Pulse Counter Watchdog Timer
Back-up RTC
Analog Interfaces
ADC
LCD Controller
DAC
Analog
Comparator
Operational
Amplifier
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
EM2 – Deep Sleep
EM3 - Stop
EM4 - Shutoff
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection
Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while
the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32LG Reference Manual.
3.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for
data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data
trace and software-generated messages.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32LG microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
3.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance
data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230
µDMA controller licensed from ARM.
3.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32LG.
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