AD9633(Rev0) 查看數據表（PDF） - Analog Devices

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AD9633
(Rev.:Rev0)

Quad, 12-Bit, 80 MSPS/105 MSPS/125 MSPS, Serial LVDS 1.8 V ADC

Analog Devices 

AD9633

VIN±x

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D0–x

D0+x

N–1

tA

tEH

tCPD

N

tEL

Data Sheet

tFCO

tFRAME

tPD

tDATA

MSB D8

D7

D6

D5

D4

D3 D2

D1

D0 MSB D8

D7

D6

D5

N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8 N–8 N–8 N–8

Figure 7. Wordwise DDR, One-Lane, 1× Frame, 10-Bit Output Mode

CLK+

SYNC

tSSYNC

tHSYNC

Figure 8. SYNC Input Timing Requirements

Rev. 0 | Page 10 of 40

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