56F8123 查看數據表（PDF） - Freescale Semiconductor

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56F8123

16-bit Digital Signal Controllers

Freescale Semiconductor 

Electrical Design Considerations

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

12.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation of the 56F8323/56F8123:

• Provide a low-impedance path from the board power supply to each VDD pin on the device, and from the

board ground to each VSS (GND) pin

• The minimum bypass requirement is to place six 0.01–0.1μF capacitors positioned as close as possible to

the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each

of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better

performance tolerances.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)

pins are less than 0.5 inch per capacitor lead

• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS

• Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade

capacitor such as a tantalum capacitor

56F8323 Technical Data, Rev. 17

Freescale Semiconductor

137

Preliminary

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