56F8123 查看數據表（PDF） - Freescale Semiconductor
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56F8123 Datasheet PDF : 140 Pages
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Signal Pins
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). In the 56F8123, after reset, each
pin must be configured for the desired function. The initialization software will configure each pin for the
function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed.
Note: Signals in italics are not available in the 56F8123 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the SCLK0/GPIOB3
pin shows that it is tri-stated during reset. If the GPIOB_PER is changed to select the GPIO function of
the pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No.
Type
State During
Reset
Signal Description
VDD_IO
6
VDD_IO
20
VDD_IO
48
VDD_IO
59
VDDA_OSC_PLL
42
Supply
Supply
VDDA_ADC
VSS
VSS
VSS
VSS
VSSA_ADC
41
Supply
11
Supply
17
44
60
39
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage regulator, if
it is enabled.
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power supply.
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
Ground — These pins provide ground for chip logic and I/O drivers.
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
19
Preliminary
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