56F8123 查看數據表（PDF） - Freescale Semiconductor
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56F8123 Datasheet PDF : 140 Pages
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Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name Pin No.
Type
State During
Reset
Signal Description
VCAP1
VCAP2
VCAP3
VCAP4
57
Supply
Supply VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2μF or greater bypass capacitor in order to
23
bypass the core logic voltage regulator, required for proper chip
operation.
5
43
When OCR_DIS is tied to VDD, (regulator disabled), these pins
become VDD_CORE and should be connected to a regulated 2.5V
power supply.
OCR_DIS
45
Note: This bypass is required even if the chip is powered with
an external supply.
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
EXTAL
46
Input
Input
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
(GPIOC0)
XTAL
Schmitt
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an EXTAL input with pull-ups disabled.
47
Output
Output Crystal Oscillator Output — This output can be connected to an
8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS.
(GPIOC1)
TCK
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Schmitt
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an XTAL input with pull-ups disabled.
53
Schmitt
Input, Test Clock Input — This input pin provides a gated clock to
Input
pulled low synchronize the test logic and shift serial data to the JTAG/EOnCE
internally port. The pin is connected internally to a pull-down resistor. A Schmitt
trigger input is used for noise immunity.
56F8323 Technical Data, Rev. 17
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Freescale Semiconductor
Preliminary
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